HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 253

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.12.0.7
July 2009
Order Number: 318378-005US
STRMIDFMT[3:2] - Stream ID Format Register
The StreamID format register is programmed such that the chipset can decode the
appropriate header bits as the StreamID for device initiated requests. A combination of
the upper Tag bits and the Function field form the StreamID. This register is
programmed in two ways: explicitly through BIOS or with the Stream Priority message
(using the StrmFmt field in the message). Since the MCH does not support stream
priority this register is RO and can not be programmed.
Offset:
7:6
5:0
Offset:
7
6:5
4
3:2
1:0
Bit
Bit
RV
RO
RO
RV
RO
RO
RO
Attr
Attr
®
5100 MCH Chipset
387h, 307h
386h, 306h
0h
000000
0
0h
0
0h
0h
Default
Default
Reserved
Num_strms_supported: Number of Streams Supported
This field identifies how many Stream ID’s the Intel
by indicating the highest StreamID value for which the device can specify a priority.
The Intel
0.
In_use: In Use
This bit indicates whether this Stream ID register is in use. A device uses this
mechanism to atomically claim exclusive ownership of this Stream ID format
register. This should be done before attempting to program it. Since Intel
MCH Chipset does not support stream priority, this is a RO register field
Reserved
Ign_fn_num: Ignore Function Number
0: When this bit is clear, the chipset only honors stream prioritization with
transactions with a Function number matching the of the function number recorded
in the REQID register and the chipset places transactions with a different Function
number into the low priority queue (LP).
1: When this bit is set, the function number captured in the REQID register is
ignored for incoming transactions. This enables the stream prioritization feature to
be implemented across multiple functions in the device.
The value of this bit does not effect the number of Function field bits that the
chipset decodes (see Function Field Size below).
Function Field Size: This field identifies how many upper bits of the PCI Express*
header’s Function field in the RequesterID should be decoded as the StreamID. For
any values other than 00, the Phantom Function capability must be employed in the
device. These bit are updated when the chipset receives a Stream Priority Message
00: No Function bits are used to identify the StreamID.
01: Function[2] is used to identify the StreamID.
10: Function[2:1] is used to identify the StreamID.
11: Function[2:0] is used to identify the StreamID.
Tag Field Size: This field identifies how many upper bits of the PCI Express*
header’s Tag field should be decoded as the StreamID. These bit are updated when
the chipset receives a Stream Priority Message.
00: No Tag bits are used to identify the StreamID.
01: Tag[7] is used to identify the StreamID.
10: Tag[7:6] is used to identify the StreamID.
11: Tag[7:5] is used to identify the StreamID.
®
5100 MCH Chipset supports only 1 stream and the highest stream ID is
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
®
5100 MCH Chipset supports
®
Datasheet
5100
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