HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 341

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.17.5.4
5.17.5.4.1
5.17.6
5.17.7
5.17.8
July 2009
Order Number: 318378-005US
When the PCI Express* interface receives a peer-to-peer memory write command,
inbound ordering rules require that it must wait until all prior inbound writes are
globally visible. The peer-to-peer write completes when the target PCI Express* port
receives the transaction in its ordered domain. The acknowledge must return to the
source PCI Express* unit quickly enough to allow the PCI Express* device to post
further peer-to-peer memory writes without any stalls on the interface.
Peer-to-peer memory write transactions are considered posted with regards to
ordering. Peer-to-peer read transactions are non-posted. Peer-to-peer transactions
must adhere to the ordering rules listed in
and
Interrupt Ordering Rules
With MSI, SAPIC and Expiate, interrupts are simply inbound non-coherent writes to the
processor. With legacy interrupts, the interrupts are Assert and Deassert messages
(also following posted write ordering rules). This enforces that the interrupt will not be
observed until all prior inbound writes are flushed to their destinations. However, the
MCH does not guarantee that the interrupt will be observed by the processor before
subsequent writes are visible to a processor.
EOI Ordering
When a processor receives an interrupt, it will process the interrupt routine. The
processor will then proceed to clear the I/O card’s interrupt register by writing to that I/
O device. In addition, for level-triggered interrupts, the processor sends an End-of-
Interrupt (EOI) special cycle (8-bit interrupt vector on D[7:0]# of the processor’s data
bus) to an IOAPIC controller south of MCH. This EOI cycle must be treated as an
outbound write with regard to ordering rules. This ensures that the EOI will not pass
any prior outbound writes. If the EOI passes the prior write to clear the register, then
the IOAPIC controller could mistakenly signal a second interrupt since the register clear
had not occurred yet.
Prefetching Policies
The MCH does not perform any speculative prefetching for PCI Express* interface
component reads. The PCI Express* component south of the Intel
is solely responsible for its own prefetch algorithms since those components are best
suited to know what tradeoffs are appropriate.
The MCH does not perform any outbound read prefetching.
PCI Express* Hide Bit
To “hide” PCI Express* ports from the OS, there is one PEXCTRL.CLASSCTRL bit for
each port. When firmware sets the write-once PEXCTRL.CLASSCTRL bit, the PCI
Express* device in the MCH changes its response to a CCR read (Class Code Register,
0600h) so that it appears to be a host bridge. The OS will not perform configuration
reads and writes to a device with its hide bit set.
No Isochronous Support
The Intel
channel (channel 0) is supported on the PCI Express* interfaces.
Table 5.17.4.14, “Peer-to-peer Configuration
®
®
5100 MCH Chipset does not support isochrony. Only the default virtual
5100 MCH Chipset
Table 5.17.4.13, “Peer-to-peer Transactions”
Cycles”.
Intel
®
5100 Memory Controller Hub Chipset
®
5100 MCH Chipset
Datasheet
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