HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 265

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

System Address Map—Intel
4.3.4
Note:
4.3.5
July 2009
Order Number: 318378-005US
The Intel
boundary. Firmware should not create data structures that span this boundary. SMM
main memory is protected from Inbound accesses.
In order to make cacheable SMM possible, the chipset must accept EWB’s and must
absorb IWB data regardless of the condition of the SMMEM# pin. The Intel
Chipset will not set the error bit EXSMRAMC.E_SMERR in this case. Because of this,
care must be used when attempting to cache SMM space. The chipset/platform cannot
protect against processors who attempt to illegally access SMM space that is modified
in another processor’s cache. Any software that creates such a condition (for example,
by corrupting the page table) will jeopardize the protective properties of SMM.
Memory Mapped Configuration (MMCFG) Region
There is one relocatable memory mapped configuration region in the Intel
Chipset. The processor bus address defines the particular configuration register to be
accessed. This configuration mechanism is atomic.
The memory mapped configuration region is compatible with the PCI Express*
enhanced configuration mechanism. The MMCFG region is a 256 MB window that maps
to PCI Express* registers on both the Intel
such as an ICH9R.
The location of this MMCFG window is defined by the SC.HECBASE register. The
HECBASE register could also be accessed through a fixed location. The default value of
SC.HECBASE maps this region such that there will be no wasted memory that is lost
behind it. The default value for the PCI Express* registers is the same as the default
value of TOLM. If this range is moved, the following recommendations will enable
reclaiming the memory that is lost to MMCFG accesses.
BIOS/software must ensure there are no outstanding configuration accesses or
memory accesses to the old and new MMCFG range addresses when relocating this
range.
An SMM program can address up to 4 GB of memory. SMM is similar to real-address
mode in that there are no privileges or address mapping. The Intel
allows the relocation of HECBASE above 4 GB. However, SMM code cannot access
extended configuration space if HECBASE is relocated above 4 GB. This is the SMM
limitation. Page Size Extension (PSE) is supported in SMM, but Page Address Extension
(PAE) support in SMM is not supported in P6 family processors. Refer to the Intel
and IA-32 Architectures Software Developer’s Manual, Volume 3, Section 24.1.
For more information on the memory mapped configuration mechanism described here,
please see
Low Memory Mapped I/O (MMIO)
This is the first of two Intel
memory mapped I/O range is defined to be between Top Of Low Memory, (TOLM) and
FE00 0000h. This low MMIO region is further subdivided between the PCI Express* and
ESI ports.
MMIO ranges for each PCI Express*/ESI device. These registers are compatible with
PCI Express* Base Specification, Rev. 1.0a and the PCI-to-PCI Bridge Architecture
1. MMCFG range is mapped to a legal location within the range between TOLM and 4
2. Put the region above 4 GB Low/Medium Memory limit and not overlapping above 4
GB. Since ranges must not overlap other legal ranges, it is safest to put this range
between TOLM and the lowest real MMIO range. (The current default is in these
ranges) OR
GB MMIO space.
®
®
Table 79, “Low Memory Mapped I/O”
5100 MCH Chipset
5100 MCH Chipset will not support a locked access that crosses an SMM
Section 4.6, “Configuration
®
5100 MCH Chipset memory mapped I/O ranges. The low
Space”.
®
5100 MCH Chipset and the south bridge,
shows the registers used to define the
Intel
®
5100 Memory Controller Hub Chipset
®
5100 MCH Chipset
®
®
5100 MCH
5100 MCH
Datasheet
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