HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 230

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HH80556KH0364M S LAGD

Manufacturer Part Number
HH80556KH0364M S LAGD
Description
Manufacturer
Intel
Datasheet

Specifications of HH80556KH0364M S LAGD

Rad Hardened
No
Lead Free Status / RoHS Status
Compliant
3.11.14
Table 75.
Intel
Datasheet
230
®
5100 Memory Controller Hub Chipset
MSIDR: Message Signaled Interrupt Data Register
IV Vector Table for DMA Errors and Interrupts
1. The term “xxxxxx” in the Interrupt vector denotes that software/BIOS initializes them and the MCH will not
Device:
Function:
Offset:
Device:
Function:
Offset:
Number of Messages Enabled by Software (MMEN)
31:16
13:11
10:8
7:0
Bit
15
14
1:0
modify any of the “x” bits since it handles only 1 message vector that is common to all events
Bit
2
Attr
RW
RW
RW
RW
RW
RV
Attr
RW
RV
8
0
5Ch
8
0
60h
Default
0000h
000
0h
0h
0h
0h
Default
00
0
Reserved.
TM: Trigger Mode
This field Specifies the type of trigger operation
0: Edge
1: level
LVL: Level
if TM is 0h, then this field is a don’t care.
Edge triggered messages are consistently treated as assert messages.
For level triggered interrupts, this bit reflects the state of the interrupt input
if TM is 1h, then:
0: Deassert Messages
1: Assert Messages
These bits are don’t care in IOxAPIC interrupt message data field specification.
DM: Delivery Mode
000: Fixed
001: Lowest Priority
010: SMI/HMI
011: Reserved
100: NMI
101: INIT
110: Reserved
111: ExtINT
IV: Interrupt Vector
The interrupt vector as programmed by BIOS/Software will be used by the Intel
5100 MCH Chipset to provide context sensitive interrupt information for different
events such as DMA Errors, DMA completions that require attention from the
processor. See
handling for DMA.
1
ADM: Address Destination Mode
0: physical
1: logical
Reserved.
Not used since the memory write is D-word aligned
Table 75, “IV Vector Table for DMA Errors and Interrupts”
Intel
(DMA completions/errors)
Description
®
Description
5100 MCH Chipset—Register Description
Events
All
Order Number: 318378-005US
xxxxxxxx
IV[7:0]
for IV
July 2009
1
®

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