HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 133

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
July 2009
Order Number: 318378-005US
Device:
Function:
Offset:
31:18
17:2
Bit
1
0
®
RWST
RWC
Attr
RW
RV
5100 MCH Chipset
19
0
17Ch
Default
1385h
3FFFh
0
0
Timeout: Completion Time out
Internal timer for handling Outbound NP completion timeouts. This varies
based on the core clock frequency and the time at which the completion
structure is loaded relative to the timeout timer which is free-running. The
bounds of this roll over can be approximated as a Minimum of 6 or Max of 7
± few cycles) since there is a 3 bit counter whose roll over is tied to the
timeout timer
For 333 MHz, the granularity of this timer viz. each increment is in the range
(9216 ns, 10,752 ns) giving a min./max value for a full face value of this
register field as (150.99 ms, 176.15 ms)
For 266 MHz, the granularity of this timer viz. each increment is in the range
(11520 ns, 13440 ns) giving a min./max value for a full face value of this
register field as (188.73 ms, 220.19 ms)
BIOS/Software needs to set this field as appropriate for handling various
timeout conditions required by the system.
Note:
Note:
Reserved
PME_TURN_OFF: Send PME Turn Off Message
When set, the Intel
all enabled PCI Express* ports excluding the ESI port. The Intel
Chipset will clear this bit once the Message is sent.
Note:
PME_TO_ACK: Received PME Timeout Acknowledge Message
The Intel
Message from all enabled PCI Express* ports excluding the ESI port.
Software will clear this bit when it handles the Acknowledge. Note that the
ESI will not generate a PME_TO_Ack. However, if a PME_TO_Ack is received
at the Intel
For example with the Intel
MHz, for SMBUS protocols, the maximum value recommended for
this field is 744h (or 1860 decimal) to achieve a 20 ms timeout
threshold (i.e., 20 ms =~ 10,752x1860) such that it provides
headroom to the chipset for the global SMBUS timeout of 25 ms.
Example: With 744h as default and 333 MHz core clock,
1. Max timeout value: If bits 31:28 were set to 744h (1860d), the
timeout delay is calculated as follows: 1860x7 (for the rollovers)
x512 (lower 9 bits)x3.0 ns (for 333 MHz) = 1860x107542=19.998
ms=~20 ms
2. Min. timeout value: If bits 31:28 were set to 744h (1860d), the
delay calculation would be like this: 1860x6 (too close to the limit,
so missed full count for one rollover) x512 (lower 9 bits) x3.0 ns (for
333 MHz)= 17.141 ms=~17 ms
In the Intel
is D3 PM state and the Link being in L2 will not respond to any
transaction to the device until it is woken up by the WAKE# signal in
the platform. Under these conditions, if software sets the
PME_Turn_OFF (bit 1) of this register, the Intel
will not send the message until the Link is brought back into L0, i.e.,
PME_TURN_OFF bit will remain set until the message is dispatched.
Furthermore, a surprise link Down error is logged.† Expected
Usage: Software should not set this bit if the link is already in L2
prior.
®
5100 MCH Chipset sets this bit when it receives a PME_TO_ACK
®
5100 MCH Chipset ESI port, it will be Master Aborted.
®
®
5100 MCH Chipset will issue a PME Turn Off Message to
5100 MCH Chipset implementation, an end device that
Description
Intel
®
5100 MCH Chipset core running at 333
®
5100 Memory Controller Hub Chipset
®
5100 MCH Chipset
®
5100 MCH
Datasheet
133