HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 138

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.10.5
Intel
Datasheet
138
®
5100 Memory Controller Hub Chipset
MSIDR[7:2,0] - MSI Data Register
The MSI Data Register (MSIDR) contains all the data (interrupt vector) related
information to route MSI interrupts.
Device:
Function:
Offset:
Device:
Function:
Offset:
31:16
13:11
11:4
10:8
1:0
Bit
Bit
15
14
3
2
Attr
Attr
RW
RW
RW
RW
RW
RW
RW
RV
RV
7-2, 0
0
5Ch
7-2, 0
0
60h
Default
Default
0000h
00h
000
0h
0h
0h
0h
0h
0h
AEXDSTID: Address Extended Destination ID
This field is not used by IA-32 processor.
ARDHINT: Address Redirection Hint
0: directed
1: redirectable
ADM: Address Destination Mode
0: physical
1: logical
Reserved.
Not used since the memory write is D-word aligned
Reserved.
TM: Trigger Mode
This field Specifies the type of trigger operation
0: Edge
1: level
LVL: Level
if TM is 0h, then this field is a don’t care.
Edge triggered messages are consistently treated as assert messages.
For level triggered interrupts, this bit reflects the state of the interrupt input
if TM is 1h, then
0: Deassert Messages
1: Assert Messages
These bits are don’t care in IOxAPIC interrupt message data field specification.
DM: Delivery Mode
000: Fixed
001: Lowest Priority
010: SMI/HMI
011: Reserved
100: NMI
101: INIT
110: Reserved
111: ExtINT
Intel
®
Description
Description
5100 MCH Chipset—Register Description
Order Number: 318378-005US
July 2009