HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 273

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

System Address Map—Intel
Table 84.
Note:
Table 85.
July 2009
Order Number: 318378-005US
SMM region
Legacy
VGA/SMM
2
A_0000h
to
B_FFFFh
SMM Memory Region Access Control from Processor
1. BRLC
2. Data access transaction other than BRLC
3. For access to TSEG region (address range between ESMMTOP - TSEG_SZ and ESMMTOP), the Intel
4. It is a programming error if D_CLS and D_OPEN are both set to 1, the Intel
The Intel
accomplished by routing memory requests from processors as a function of transaction
request address, code or data access, the SMMEM# signal accompanying request and
the settings of the SC.SMRAMC, SC.EXSMRC, and SC.BCTRL registers.
“Decoding Processor Requests to SMM and VGA Spaces”
Chipset’s routing for each case. Illegal accesses are either routed to the ESI bus where
they are Master Aborted or are blocked with error flagging. SMMEM# only affects the
Intel
D_CLS only applies to the legacy (A_0000-B_FFFFh) SMM region. The bold values
indicate the reason SMM access was granted or denied.
If a spurious inbound access targets the enabled SMM range (viz., legacy, High SMM
Memory and Extended SMRAM (T-segment)), then it will be Master-aborted. The
EXSMRAMC.E_SMERR register field (Invalid SMRAM) is set for accesses to the High
SMM Memory and Extended SMRAM (T-segment)). Refer to
Disposition for Inbound Transactions.”
Decoding Processor Requests to SMM and VGA Spaces (Sheet 1 of 2)
G_SMRAME
Transaction
MCH Chipset will route to identical system memory by definition (as TSEG is not enabled).
undefined. The Intel
Address
Range
®
0
1
1
1
1
1
1
1
1
1
5100 MCH Chipset behavior if it falls in an enabled SMM space. Note that the
3
4
®
®
5100 MCH Chipset
5100 MCH Chipset prevents illegal processor access to SMM memory. This is
D_LCK
x
0
0
0
0
x
1
1
1
1
A_0000h
to
B_FFFFh
®
5100 MCH Chipset could master abort SMM access.
SMM Memory
Address
D_CLS
Range
0
0
1
1
0
1
0
1
x
x
D_OPEN
x
0
0
1
0
1
x
0
x
0
Control
x
yes
no
yes
Access
SMM
1
SMMEM#
0
1
1
1
x
0
1
x
1
x
0
0
1
1
x
1
x
0
Intel
x
x
x
x
Code Access to
SMM Memory
illegal settings
®
defines the Intel
5100 Memory Controller Hub Chipset
x
x
x
x
Table 86, “Address
yes
yes
yes
yes
yes
no
no
no
no
®
5100 MCH Chipset’s behavior is
to the VGA-enabled port (in
BCTRL);
otherwise, ESI
to SMM memory
1
yes (H_SMM, TSEG)
yes (H_SMM, TSEG)
Table 85,
no (legacy SMM)
no (legacy SMM)
Routing
Data Access to
SMM Memory
illegal settings
®
3
5100 MCH
yes
yes
yes
no
no
no
no
Datasheet
®
5100
2
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