HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 113

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.8.1
July 2009
Order Number: 318378-005US
PEXCMD[7:2,0]- Command Register
This register defines the PCI 2.3 compatible command register values applicable to PCI
Express* space.
Device:
Function:
Offset:
15:11
Bit
10
9
8
7
6
5
4
3
®
Attr
5100 MCH Chipset
RW
RW
RW
RV
RO
RO
RO
RO
RO
7-2, 0
0
04h
Default
0h
0
0
0
0
0
0
0
0
Reserved. (by PCI-SIG)
INTxDisable: Interrupt Disable
Controls the ability of the PCI Express* port to generate INTx messages to
the ESI port to external interrupt controller where an interrupt can be
generated to the CPU.
This bit does not affect the ability of the Intel
interrupt messages received at the PCI Express* port. However, this bit
controls the generation of legacy interrupts to the ESI port for PCI
Express* errors detected internally in this port (e.g., Malformed TLP, CRC
error, completion timeout etc.) or when receiving root port error messages
or interrupts due to HP/PM events generated in legacy mode within the
Intel
“INTP[7:2,0] - Interrupt Pin Register”
1: Legacy Interrupt mode is disabled
0: Legacy Interrupt mode is enabled
FB2B: Fast Back-to-Back Enable
Not applicable to PCI Express* and is hardwired to 0
SERRE: SERR Message Enable
his field handles the reporting of fatal and non-fatal errors by enabling the
error pins ERR[2:0].
1: The Intel
0: The Intel
errors.
The errors are also enabled by the PEXDEVCTRL register in
3.8.11.4, “PEXDEVCTRL[7:2,0] - PCI Express* Device Control Register.”
In addition, for Type 1 configuration space header devices, e.g., Virtual
PCI-to-PCI bridge), this bit, when set, enables transmission of
ERR_NONFATAL and ERR_FATAL error messages
Express* interface. This bit does not affect the transmission of forwarded
ERR_COR messages. Refer to the Intel
Model.
IDSELWCC: IDSEL Stepping/Wait Cycle Control
Not applicable to PCI Express*. Hardwired to 0.
PERRE: Parity Error Response Enable
When set, this field enables parity checking.
VGAPSE: VGA palette snoop Enable
Not applicable to PCI Express*. Hardwired to 0.
MWIEN: Memory Write and Invalidate Enable
Not applicable to PCI Express*. Hardwired to 0.
SCE: Special Cycle Enable
Not applicable to PCI Express*. Hardwired to 0.
®
5100 MCH Chipset. Refer to the INTP register in
®
®
5100 MCH Chipset is disabled from generating fatal/non-fatal
5100 MCH Chipset is enabled to send fatal/non-fatal errors.
Description
Intel
®
for interrupt routing to ESI port.
®
5100 Memory Controller Hub Chipset
5100 MCH Chipset RAS Error
®
5100 MCH Chipset to route
1
forwarded from the PCI
Section 3.8.8.27,
Section
Datasheet
113