HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 343

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.19.1
Table 109.
5.19.1.1
July 2009
Order Number: 318378-005US
Intel
The Intel
Table 109, “Intel® 5100 Memory Controller Hub Chipset Reset Classes.”
Intel
Power-Good Mechanism
The initial boot of an Intel
mechanism. The voltage sources from all platform power supplies are routed to a
system component which tracks them as they ramp-up, asserting the platform or
system PwrGd signal a fixed interval (> 2 ms) after the last voltage reference has
stabilized. There are no requirements within the MCH regarding the precise sequencing
of power-supply ramps, thus the platform should initialize properly regardless of the
order in which supplies stabilize.
Both the Intel
dedicated pins, PWRGOOD and PWROK respectively, as asynchronous inputs, meaning
that there is no assumed relationship between the assertion or deassertion of PwrGd
and any system reference clock. When PwrGd is deasserted all platform subsystems
are held in their reset state. This is accomplished by various mechanisms on each of
the different interfaces. The MCH will hold itself in a power-on reset state when
PWRGOOD is deasserted. The ICH9R is expected to assert its PLTRST# output and
maintain its assertion for 1 ms after power is good, PWROK is asserted. The PLTRST#
output from ICH9R is expected to drive the RESETI# input pin on the Intel
Chipset, which will in turn hold the processor complex in reset via assertion of the
FSB{0/1}RESET# FSB signals.
The PCI Express* attached devices and any hierarchy of components underneath them
are held in reset via implicit messaging across the PCI Express* interface. The MCH is
the root of the hierarchy, and will not engage in link training until power is good and the
internal power-on reset has deasserted.
A system PwrGd reset will clear all internal state machines and logic, and initialize all
registers to their default states, including “sticky” error status bits that are persistent
through all other reset classes. To eliminate potential system reliability problems, all
devices are also required to either tristate their outputs or to drive them to “safe” levels
during a power-on reset.
The only system information that will remain after a system PwrGd reset is either
contained in battery-backed or non-volatile storage.
Power-Good
Hard
Processor-
only
Targeted
BINIT#
Type
®
®
5100 Memory Controller Hub Chipset Reset Classes
®
5100 Memory Controller Hub Chipset Reset Types
®
5100 MCH Chipset differentiates among five types of reset as defined in
PWRGOOD Input Pin
RESETI# Input Pin,
Configuration Write
Configuration Write
Configuration Write
Internal Error
Handling Propagated
via FSB BINIT# pin
5100 MCH Chipset
®
Mechanism
5100 MCH Chipset and the ICH9R receive the system PwrGd signal via
®
5100 MCH Chipset is facilitated by the Power-Good (PwrGd)
Propagated throughout the system hierarchy. Resets all logic and state
machines, and initializes all registers to their default states (sticky and
non-sticky). Tristates all MCH outputs, or drives them to “safe” levels.
Propagated throughout the system hierarchy. Resets all logic and state
machines, and initializes all non-sticky registers to their default states.
Tristates all MCH outputs, or drives them to “safe” levels.
Propagated to all processors via the FSB{0/1}RESET# pins on the FSB.
The MCH does not undergo an internal reset.
Propagated down the targeted PCI Express* port hierarchy. Treated as
a “Hard” reset by all affected components, clearing all machine state
and non-sticky configuration registers.
Propagated to all FSB attached components (the MCH and up to two
processors). Clears the IOQ, and resets all FSB arbiters and state
machines to their default states. Not recoverable.
Effect/Description
Intel
®
5100 Memory Controller Hub Chipset
®
5100 MCH
Datasheet
343