HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 375

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
Table 123.
July 2009
Order Number: 318378-005US
M5
M6
M10
M11
M12
M14
M15
M16
M18
M20
M21
Notes:
1.
2.
ERR #
MCH
in
IO3 error logging in Intel
ECN (Dec. 2004). However, PEXLNKSTS.TERR provides training indication.
Aliased uncorrectable errors are uncorrectable errors that masquerades as correctable errors to the Memory Controller.
Aliased
Uncorrectable
Spare-Copy
Data ECC Error
Aliased
Uncorrectable
Patrol Data ECC
Error
Non-Aliased
Uncorrectable
Demand Data
ECC Error
Non-Aliased
Uncorrectable
Spare-Copy
Data ECC Error
Non-Aliased
Uncorrectable
Patrol Data ECC
Error
Correctable
Demand Data
ECC Error.
Correctable
Spare-Copy
Data ECC Error
Correctable
Patrol Data ECC
Error
SPD protocol
Error
Rank-Spare
Copy start
Rank-Spare
Copy complete
Error Name
Intel
®
5100 Memory Controller Hub Chipset Error List (Sheet 7 of 7)
During a Sparing copy
read from the failing rank
the MCH determined that a
normally “correctable”
error could be an aliased
(x4 only) full device failure
plus an additional single
bit error.
During a Patrol Scrub, the
MCH determined that a
normally “correctable”
error could be an aliased
(x4 only) full device failure
plus an additional single
bit error.
The MCH detected
uncorrectable data on a
demand read.
The MCH detected
uncorrectable data rank
during a spare copy read.
During a patrol scrub, the
MCH detected
uncorrectable data.
The MCH detected
correctable data.
The MCH detected
correctable data from the
failing rank during a spare
copy.
During a patrol scrub, the
MCH detected correctable
data.
The MCH detected an SPD
interface error.
Triggered Spare copy
Spare copy completed
normally
®
5100 MCH Chipset
®
5100 MCH Chipset has been defeatured due to PCI Express* Base Specification, Rev. 1.0a
Definition
Error
Type
Corr
Corr
Corr
Corr
Corr
Corr
Rec
Rec
Rec
Rec
Rec
VALIDLOG[1:0], RECMEMA
VALIDLOG[1:0], RECMEMA
VALIDLOG[1:0], RECMEMA
VALIDLOG[1:0], RECMEMA
VALIDLOG[1:0], RECMEMA
VALIDLOG[1:0], REDMEMA
VALIDLOG[1:0], REDMEMA
VALIDLOG[1:0], REDMEMA
NERR_NF_MEM and
NERR_NF_MEM and
NERR_NF_MEM and
NERR_NF_MEM and
NERR_NF_MEM and
NERR_NF_MEM and
NERR_NF_MEM and
NERR_NF_MEM and
FERR_NF_MEM/
FERR_NF_MEM/
FERR_NF_MEM/
FERR_NF_MEM/
FERR_NF_MEM/
FERR_NF_MEM/
FERR_NF_MEM/
FERR_NF_MEM/
FERR_NF_MEM/
NERR_NF_MEM
and RECMEMB
and RECMEMB
and RECMEMB
and RECMEMB
and RECMEMB
and REDMEMB
and REDMEMB
and REDMEMB
Log Register
SPCPC[1:0]
SPCPS[1:0]
Intel
®
5100 Memory Controller Hub Chipset
See
Recovery Scheme” on
page
See
Recovery Scheme” on
page
See
Recovery Scheme” on
page
See
Recovery Scheme” on
page
See
Recovery Scheme” on
page
See
Recovery Scheme” on
page
See
Recovery Scheme” on
page
See
Recovery Scheme” on
page
Successive correction
attempts performed by
software.
Start spare copy
No Action
Figure 54, “DDR Error
Figure 54, “DDR Error
Figure 54, “DDR Error
Figure 54, “DDR Error
Figure 54, “DDR Error
Figure 54, “DDR Error
Figure 54, “DDR Error
Figure 54, “DDR Error
376.
376.
376.
376.
376.
376.
376.
376.
Cause/Actions
Datasheet
375