HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 61

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Signal Description—Intel
2.10.1.2
Figure 6.
2.10.1.3
Figure 7.
July 2009
Order Number: 318378-005US
Note:
Synchronized RESETI#
Synchronized RESETI#
Synchronized RESETI# is the RESETI# signal synchronized with the necessary internal clock domain, the PLLs are the
internal PLLs locking to the BUSCLK signal and POC is Power-On Configuration, see
processor RESET#
processor RESET#
Sticky Bit Enable
SYRE.SAVCFG
PCI Express*
PCI Express*
PWRGOOD
Sticky Bits
RESETI#
BUSCLK
RESETI#
INITIN#
BUSCLK
Events
Events
Power Good
The PWRGOOD reset sequence is illustrated in
PWRGOOD
Hard Reset
The Hard Reset sequence is illustrated in
Hard Reset
PLL's
PLL's
POC
POC
ESI
ESI
®
T2
5100 MCH Chipset
Straps
active
T9
T3
T4
sampled
T10
Straps
T7
T8
T10
T9
inactive
Straps
Figure 7, “Hard Reset.”
downloaded
Fuses
Figure 6, “PWRGOOD.”
T11
T11
Intel
T13
initialization
T12
T13
initialization
®
Array Init
Section 1.1,
Done
T12
5100 Memory Controller Hub Chipset
Array Init
Done
ESI handshake started
T15
“Terminology”.
ESI handshake started
T15
full operation
full operation
T14
T14
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Datasheet
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