HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 65

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.0
3.1
Table 26.
July 2009
Order Number: 318378-005US
Register Description
The Intel
via the host processor I/O address space:
The MCH supports PCI configuration space accesses using the mechanism denoted as
Configuration Mechanism 1 as defined in the PCI Local Bus Specification, Rev. 2.3. All
the registers are organized by bus, device, function, etc., as defined in the PCI
Express* Base Specification, Rev. 1.0a. The MCH supports registers in PCI Express*
extended space. All registers in the Intel
In addition, the MCH registers can be accessed by a memory mapped register access
mechanism (as MMIO), a PCI configuration access mechanism (only PCI space
registers), and register access mechanisms through the SMBus. The memory mapped
access mechanism is further broken down into different ranges. The internal registers
of this chipset can be accessed in 8-bit, 16-bit, or 32-bit quantities, with the exception
of CFGADR which can only be accessed as a 32-bit. All multi-byte numeric fields use
“little-endian” ordering (i.e., lower addresses contain the least significant parts of the
field).
In addition, the MCH can forward accesses to all PCI/PCI Express* configuration
registers from the ICH or other PCI Express* bridges through the same mechanisms.
Register Terminology
Registers and register bits are assigned one or more of the attributes described in
Table
register. Sticky bits retain their states across hard resets. All other bits are set to
default values by a hard reset.
Register Attributes Summary Table
RO
WO
RW
RC
RCW
• Control registers I/O mapped into the processor I/O space that controls access to
• Internal configuration registers residing within the MCH are partitioned into logical
PCI configuration spaces.
device register sets (“logical” since they reside within a single physical device). The
first register set is dedicated to MCH functionality (Device 0 controls PCI bus 0, i.e.,
DRAM configuration, other chipset operating parameters, and optional features).
Term
26. These attributes define the behavior of the bit(s) that are contained within a
®
®
5100 MCH Chipset
5100 MCH Chipset contains sets of software accessible registers accessed
Read Only. If a register bit is read only, the hardware sets its state. The bit may be read
by software. Writes to this bit have no effect.
Write Only. The register bit is not implemented as a bit. The write causes some
hardware event to take place.
Read/Write. A register bit with this attribute can be read and written by software.
Read Clear: The bit or bits can be read by software, but the act of reading causes the
value to be cleared.
Read Clear/Write: A register bit with this attribute will get cleared after the read. The
register bit can be written.
®
5100 MCH Chipset appear on PCI Bus #0.
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
65