HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 180

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.13.16
3.8.13.17
3.8.13.18
Intel
Datasheet
180
®
5100 Memory Controller Hub Chipset
FERR_FAT_INT - Internal First Fatal Error Register
FERR_FAT_INT latches the first MCH internal fatal error. All subsequent errors get
logged in the NERR_FAT_INT.
FERR_NF_INT - Internal First Non-Fatal Error Register
NERR_FAT_INT - Internal Next Fatal Error Register
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
4:2
7:3
7:4
7:1
7:3
7:4
Bit
Bit
Bit
Bit
5
1
0
3
2
1
0
0
3
2
1
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWST
RWST
RWST
Attr
Attr
Attr
Attr
RV
RV
RV
RV
RV
RV
RV
RV
16
0
49Ah, 19Ah
16
2
C0h
16
2
C1h
16
2
C2h
Default
Default
Default
Default
0h
0h
0h
1
1
1
0
0
0
0
0h
0h
0h
0
0
0
0
F6Msk: Data Parity Error
Reserved
F2Msk: Unsupported Processor Bus Transaction
F1Msk: Request/Address Parity Error
Reserved
Reserved
B4Err: Virtual Pin Port Error (VPP_PEX)
B3Err: Coherency Violation Error for WEWB
Reserved
B1Err: DM Parity Error (Data Manager)
Reserved
Reserved
B4Err: Virtual Pin Port Error (VPP_PEX)
B3Err: Coherency Violation Error (COH) for EWB
Reserved
Reserved
B5Err: Single Address Map Error (COH)
Intel
®
5100 MCH Chipset—Register Description
Description
Description
Description
Description
Order Number: 318378-005US
July 2009