HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 117

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.8.8
3.8.8.9
3.8.8.10
3.8.8.11
July 2009
Order Number: 318378-005US
EXP_ROM[0]: Expansion ROM Registers
The ESI port (device 0, function 0) does not implement any Base address registers in
the Intel
address register is defined in offset 30h. Also no Cardbus CIS pointer is defined in
offset 28h. The MIN_GNT (offset 3Eh) and MAX_LAT (3Fh) registers are also not
implemented as they are not applicable to the ESI interface.
PBUSN[7:2] - Primary Bus Number
This register identifies the bus number on the primary side (MCH) of the PCI Express*
port.
SBUSN[7:2] - Secondary Bus Number
This register identifies the bus number assigned to the secondary side (PCI Express*)
of the “virtual” PCI-to-PCI bridge. This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to devices connected to PCI
Express*.
SUBUSN[7:2] - Subordinate Bus Number
This register identifies the subordinate bus (if any) that resides at the level below the
secondary PCI Express* interface. This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to devices subordinate to the
secondary PCI Express* port.
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
7:0
7:0
7:0
Bit
Bit
Bit
®
®
Attr
Attr
Attr
RW
RW
RO
5100 MCH Chipset
5100 MCH Chipset from offset 10h to 24h. Similarly no Expansion ROM base
2-3, 4-7
0
18h
2-3, 4-7
0
19h
2-3, 4-7
0
1Ah
Default
Default
Default
00h
00h
00h
PBUSNUM: Primary Bus Number
Configuration software typically programs this field with the number of the bus
on the primary side of the bridge. Since the PCI Express* virtual PCI-to-PCI
bridge is an internal device and its primary bus is consistently 0, these bits are
read only and are hardwired to 0.
SECBUSNUM: Secondary Bus Number
This field is programmed by configuration software with the lowest bus
number of the busses connected to PCI Express*. Since both bus 0, device 1
and the PCI-to-PCI bridge on the other end are considered by configuration
software to be PCI-to-PCI bridges, this bus number will consistently
correspond to the bus number assigned to the PCI Express* port
SUBBUSNUM: Subordinate Bus Number
This register is programmed by configuration software with the number of the
highest subordinate bus that is behind the PCI Express* port.
Description
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
117