HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 125

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
July 2009
Order Number: 318378-005US
Device:
Function:
Offset:
Bit
8
7
6
5
4
3
®
Attr
RW
RW
RW
RO
RO
RO
5100 MCH Chipset
7-2
0
3Eh
Default
0
0
0
0
0
0
PDT: Primary Discard Timer
Not applicable to PCI Express*. This bit is hardwired to 0.
FB2BEN: Fast Back-to-Back Enable
Not applicable to PCI Express*. This bit is hardwired to 0.
SBUSRESET: Secondary Bus Reset
1: Setting this bit causes a hot reset on the link for the corresponding PCI
Express* port and the PCI Express* hierarchy domain subordinate to the port.
This sends the LTSSM into the Hot-Reset state, which necessarily implies a
reset to the downstream device and all subordinate devices.
The mechanism to reset the downstream device is utilizing the TS1/TS2 “link
reset” bit (bit number 0 of symbol 5). It is recommended for software/BIOS
that the SBUSRESET field be held asserted for a minimum of 2 ms to ensure
that the Link enters the Hot-Reset state from L0 or L1/L2.
Software can also poll the PEXLNKSTS.LNKTRG bit for a deasserted condition
to determine if the Hot-Reset state has been entered at which point it can
clear the SBUSRESET field to train the link.
When this SBUSRESET bit is cleared after the MCH enters the “Hot-Reset”
state, the Intel
state and then train the link (polling, configuration, L0 (link-up)) after sending
at least 2 TS1 and receiving 1 TS1 with the HotReset bit set in the training
control field of TS1 and waiting for 2 ms in the Hot-Reset state. The 2 ms stay
in the Hot-Reset state is enforced by the chipset LTSSM for the PCI Express*
hierarchy to reset.
If the SBUSRESET is held asserted even after the 2 ms timeout has expired,
the Intel
Hence it is necessary for software to clear this register appropriately to bring
the link back in training.
Note also that a secondary bus reset will not in general reset the primary side
configuration registers of the targeted PCI Express* port. This is necessary to
allow software to specify special training configuration, such as entry into
loopback mode.
0: No reset happens on the PCI Express* port.
MAMODE: Master Abort Mode
Not applicable to PCI Express*. This bit is hardwired to 0.
VGA16bdecode: VGA 16-bit decode
This bit enables the virtual PCI-to-PCI bridge to provide 16-bit decoding of
VGA I/O address precluding the decoding of alias addresses every 1 kB. The I/
O addresses decoded is in the range of 03B0h to 03BBh or 03C0h to 03DFh
within the first 1 kB I/O space.
0: execute 10-bit address decodes on VGA I/O accesses.
1: execute 16-bit address decodes on VGA I/O accesses.
This bit only has meaning if bit 3 (VGAEN) of this register is also set to 1,
enabling VGA I/O decoding and forwarding by the bridge.
This read/write bit enables system configuration software to select between
10- and 16-bit I/O address decoding for all VGA I/O register accesses that are
forwarded from the primary to secondary whenever the VGAEN is set to 1.
VGAEN: VGA Enable
Controls the routing of CPU initiated transactions targeting VGA compatible I/
O and memory address ranges. This bit may only be set for one PCI Express*
port.
®
5100 MCH Chipset will continue to maintain the Hot-Reset state.
®
5100 MCH Chipset will initiate operations to move to “detect”
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
125