HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 367

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.22.3
5.22.4
5.22.5
Table 122.
July 2009
Order Number: 318378-005US
SMBus Clock
The SMBus clock is synchronized to the core clock. Data is driven into the Intel
MCH Chipset with respect to the serial clock signal. Data received on the data signal
with respect to the clock signal will be synchronized to the core using a metastability
hardened synchronizer guaranteeing an MTBF greater than 10
can not be active until 10 mS after RESETI# deassertion. When inactive, the serial
clock should be deasserted (High). The serial clock frequency is 100 kHz.
GPIO Serial Bus Clock
The transmitted 100 kHz Virtual Pin Interface (VPI) clock (one of the SMBCLKs) is
derived from the core clock.
Clock Pins
Clock Pins
CORECLKP
CORECLKN
PECLKP
PECLKN
CH{0/1}_DCLKP
CH{0/1}_DCLKN
PSEL[2:0]
VCCDDR
FSBVCCA
PEVCCA
PEVSSA
COREVCCA
COREVSSA
TCK
GPIOSMBCLK
CFGSMBCLK
SPD0SMBCLK
XDPSTBP#
XDPSTBN#
FSB{0/1}STBP[3:0]#
FSB{0/1}STBN[3:0]#
FSB{0/1}ADSTB[1:0]#
Pin Name
®
5100 MCH Chipset
Processor bus clock
Processor bus clock (Complement)
PCI Express* clock
PCI Express* clock (Complement)
DDR clocks
DDR clocks (Complement)
BUSCLK:CORECLK Bus Ratio Selector
Analog power supply for DDR PLLs
Analog power supply for processor bus PLL
Analog power supply for PCI Express* PLLs
Analog ground for PCI Express* PLLs
Analog power supply for Core PLL
Analog ground for Core PLL
TAP clock
GPIO (Virtual Pin Port) clock
SMBus clock
SMBus clock
Debug bus data strobe
Debug bus data strobe (Complement)
Processor bus data strobes
Processor bus data strobes (Complements)
Processor bus address strobes
Pin Description
Intel
®
5100 Memory Controller Hub Chipset
7
years. The serial clock
®
Datasheet
5100
367