HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 141

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.11.4
July 2009
Order Number: 318378-005US
PEXDEVCTRL[7:2,0] - PCI Express* Device Control Register
The PCI Express* Device Control register controls PCI Express* specific capabilities
parameters associated with this port.
Device:
Function:
Offset:
11:9
8:6
4:3
2:0
Bit
12
5
®
Attr
RO
RO
RO
RO
RO
RO
5100 MCH Chipset
7-2, 0
0
70h
Default
111
111
001
0h
0
0
ABPD: Attention Button Present
This bit when set indicates that an Attention Button is implemented.
0: ABPD is disabled in the Intel
1: Reserved
EPL1AL: Endpoint L1 Acceptable Latency
This field indicates the acceptable latency that an Endpoint can withstand due
to the transition from L1 state to the L0 state.
000: Less than 1µs
001: 1 µs to less than 2 µs
010: 2 µs to less than 4 µs
011: 4 µs to less than 8 µs
100: 8 µs to less than 16 µs
101: 16 µs to less than 32 µs
110: 32 µs to 64 µs
111: More than 64 µs
The Intel
and is set to the maximum value for safety
EPL0AL: Endpoints L0s Acceptable Latency
This field indicates the acceptable latency that an Endpoint can withstand due
to the transition from L0s state to the L0 state.
000: Less than 64 ns
001: 64 ns to less than 128 ns
010: 128 ns to less than 256 ns
011: 256 ns to less than 512 ns
100: 512 ns to less than 1 µs
101: 1 µs to less than 2 µs
110: 2 µs to 4 µs
111: More than 4 µs
Note that the Intel
and for backup, this field is set to the maximum value.
ETFS: Extended Tag Field Supported
This field indicates the maximum supported size of the Tag field.
0: In the Intel
PFS: Phantom Functions Supported
This field indicates the number of most significant bits of the function number
portion of Requester ID in a TLP that are logically combined with the Tag
identifier.
0: For root ports, no function number bits for phantom functions are
supported
MPLSS: Max Payload Size Supported
This field indicates the maximum payload size that the PCI Express* port can
support for TLPs.
001: 256 bytes max payload size
Others - Reserved
Note that the Intel
bytes payload (e.g., writes, read completions) for each TLP and violations will
be flagged as PCI Express* errors
®
5100 MCH Chipset does not support Endpoint L1 acceptable latency
®
5100 MCH Chipset, only 5-bit Tag field is supported
®
®
5100 MCH Chipset only supports up to a maximum of 256
5100 MCH Chipset does not support L0s implementation
®
Description
5100 MCH Chipset.
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
141