HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 59
HH80556KH0364M S LAGD
Manufacturer Part Number
HH80556KH0364M S LAGD
Description
Manufacturer
Intel
Datasheet
1.HH80556KH0364M_S_LAGD.pdf
(434 pages)
Specifications of HH80556KH0364M S LAGD
Rad Hardened
No
Lead Free Status / RoHS Status
Compliant
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Signal Description—Intel
2.9
Figure 4.
July 2009
Order Number: 318378-005US
Power Rails
PWRGOOD
RESETI#
BUSCLK
Intel
Requirements
Power Plane and Sequencing Requirements:
Intel
• Clock Valid Timing:
• BUSCLK must be valid at least 2 ms prior to rising edge of PWRGOOD. See
5.22.1, “Reference Clocks”
®
®
®
5100 Memory Controller Hub Chipset Clock and Reset Requirements
5100 MCH Chipset
5100 Memory Controller Hub Chipset Sequencing
~100ms
2ms
(T1)
for definition of BUSCLK.
1ms
(T9)
Intel
®
5100 Memory Controller Hub Chipset
0913061242
Section
Datasheet
59
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