HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 30

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 2.
1.3
Intel
Datasheet
30
®
5100 Memory Controller Hub Chipset
Related Documents (Sheet 2 of 2)
Intel
In a Intel
interfaces, two DDR2 memory channels, six x4 PCI Express* bus interfaces
configurable to form x4, x8 or x16 ports, an Enterprise South Bridge Interface (ESI),
and three SMBus interfaces for system management, PCI Hot Plug* control and DIMM
Serial Presence Detect (SPD). The Intel
has DMA Engine (Crystal Beach [CB]) capabilities and supports Intel
Technology (Intel
based System Block Diagram”
based platform.
This document contains product information and/or design guidelines specific to
component manufacturing steppings. For more information on correlating product
marking information to manufacturing stepping, please refer to the Intel
Memory Controller Hub Chipset Specification Update.
Intel
Intel
Update
Intel
Applications Thermal Design Guide
Intel
Memory Controller Hub Chipset for Communications and Embedded
Applications – Platform Design Guide
Intel
Controller Hub Chipset – Platform Design Guide
PCI Express* Base Specification, Rev. 1.0a
PCI Local Bus Specification, Rev. 2.3
Quad-Core and Dual-Core Intel
with Intel
Communications, Embedded, and Storage Applications – Platform
Design Guide
Quad-Core Intel
Quad-Core Intel
Quad-Core Intel
Design Guidelines
Quad-Core Intel
Quad-Core Intel
Quad-Core Intel
Design Guidelines
Quad-Core Intel
Thermal and Mechanical Design Guidelines
RS - Intel
RS - Intel
Xeon
System Management Bus (SMBus) Specification, Version 2.0
Notes:
1.
®
®
®
®
®
®
Core™2 Duo Processor, Intel
Core™2 Extreme Processor on 45-nm Process Specification
Core™2 Duo Processors on 45-nm process for Embedded
Core™2 Duo Processors T9400 and SL9400 and Intel
Core™2 Duo Processor T9400 and Intel® 5100 Memory
Processor External HW Spec
®
Contact your Intel sales representative. Some documents may not be available at this time.
®
®
®
®
5100 Memory Controller Hub Chipset for
5100 Memory Controller Hub Chipset BIOS Specification
Core™ Microarchitecture, Intel
5100 Memory Controller Hub Chipset Overview
5100 MCH Chipset-based platform, the MCH provides two FSB processor
®
®
®
®
®
®
®
Xeon
Xeon
Xeon
Xeon
Xeon
Xeon
Xeon
®
®
®
®
®
®
®
®
I/OAT).
Processor 5300 Series Datasheet
Processor 5300 Series Specification Update
Processor 5300 Series Thermal/Mechanical
Processor 5400 Series Datasheet
Processor 5400 Series Specification Update
Processor 5400 Series Thermal/Mechanical
Processor L5318 in Embedded Applications
Document
®
Xeon
Figure 1, “Intel® 5100 Memory Controller Hub Chipset-
®
Core™2 Solo Processor and
®
shows a block diagram of a Intel
Processor 5000 Sequence
®
Pentium
®
5100 Memory Controller Hub Chipset device
®
4, and Intel
®
5100
®
Intel
http://www.intel.com/
http://www.intel.com/
Note
Note
http://www.pcisig.com/specifications/
pciexpress/
http://www.pcisig.com/specifications/
conventional/
Note
http://www.intel.com/
http://www.intel.com/
http://www.intel.com/
http://www.intel.com/
http://www.intel.com/
http://www.intel.com/
http://www.intel.com/
Note
Note
http://www.smbus.org/specs/
®
5100 MCH Chipset—Introduction
Document Number/Location
1
1
1
1
1
Order Number: 318378-005US
®
5100 MCH Chipset-
®
I/O Acceleration
®
(320121)
(320028)
(315569)
(315338)
(315794)
(318589)
(318585)
(318611)
(318474)
5100
July 2009