HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 355

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
Table 112.
5.20.5.1
Table 113.
Note:
July 2009
Order Number: 318378-005US
Each component on the Intel
5100 MCH Chipset component addresses are defined in
Intel® 5100 Memory Controller Hub Chipset-based Platform.”
SMBus Address for Intel
Platform
Supported SMBus Commands
Intel
Version 2.0 slave ports support the following six SMBus commands:
Sequencing these commands will initiate internal accesses to the component’s
configuration registers.
Each configuration read or write first consists of an SMBus write sequence which
initializes the Bus Number, Device Number, etc. The term sequence is used since these
variables may be written with a single block write or multiple word or byte writes. Once
these parameters are initialized, the SMBus master can initiate a read sequence (which
performs a configuration read) or a write sequence (which performs a configuration
write).
Each SMBus transaction has an 8-bit command driven by the master. The format for
this command is illustrated in
SMBus Command Encoding
The Begin bit indicates the first transaction of a read or write sequence.
The End bit indicates the last transaction of a read or write sequence.
The PEC_en bit enables the 8-bit Packet Error Code (PEC) generation and checking
logic.
The Internal Command field specifies the internal command to be issued by the SMBus
slave logic. Note that the Internal Command must remain consistent during a sequence
that accesses a configuration register. Operation cannot be guaranteed if it is not
consistent when the command setup sequence is done.
The SMBus Command field specifies the SMBus command to be issued on the bus. This
field is used as an indication of the length of transfer so the slave knows when to
expect the Packet Error Code packet.
Reserved bits should be written to zero to preserve future compatibility.
Packet Error Code (PEC) is not a supported feature; see
Field.”
Begin
• Block Write
• Block Read
7
®
Intel
5100 MCH Chipset components System Management Bus (SMBus) Specification,
End
®
®
Component
5100 MCH Chipset
5100 MCH Chipset
6
Rsvd
5
®
PEC_en
®
5100 Memory Controller Hub Chipset-based
Table 113, “SMBus Command Encoding”
4
5100 MCH Chipset must have a unique address. Intel
• Word Write
• Word Read
SMBus Address (7:1)
Internal Command:
00 - Read DWord
01 - Write Byte
10 - Write Word
11 - Write DWord
1100_000
3:2
Intel
Table 112, “SMBus Address for
Section 5.20.3.1, “Command
®
5100 Memory Controller Hub Chipset
• Byte Write
• Byte Read
SMBus Command:
00 - Byte
01 - Word
10 - Block
11 - Rsvd
below.
1:0
Datasheet
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®