HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 235

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.11.21.2
July 2009
Order Number: 318378-005US
FERR_CHANERR - First Error Channel Error Register
The Channel Error Register records the first error conditions occurring within a given
DMA channel. The channel number in error is recorded in the FERR_CHANSTS register
defined in
Device:
Function:
Offset:
15
14
13
12
11
10
9
8
7
6
5
Bit
RO
RO
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RO
RWCST
RWCST
Attr
®
Section
5100 MCH Chipset
8
0
80h
0
0
0
0
0
0
0
0
0
0
0
Default
3.11.21.4.
FERR_Unaffiliated_Error_DMA15: FERR_Unaffiliated_Error_DMA15
The Intel
FERR_Soft_Error_DMA14: FERR_Soft_Error_DMA14
The Intel
FERR_Interrupt_Configuration Error_DMA13:
FERR_Interrupt_Configuration Error_DMA13
The DMA channel sets this bit indicating that the interrupt registers were not
configured properly when the DMA channel attempted to generate an interrupt.
FERR_Completion_Address Error_DMA12: FERR_Completion_Address
Error_DMA12
The DMA channel sets this bit indicating that the completion address register was
configured to an illegal address
checked and set by the DMA Engine during execution, i.e., when the completion
address is fetched for status update.
FERR_Descriptor_Length Error_DMA11: FERR_Descriptor_Length
Error_DMA11
The DMA channel sets this bit indicating that the current transfer has an illegal
length field value (either zero or exceeded the maximum length allowed in the
XFERCAP.trans_cap field in
FERR_Descriptor_Control_Error_DMA10:
FERR_Descriptor_Control_Error_DMA10
The DMA channel sets this bit indicating that the current descriptor has an illegal
control field value in the “desc_control” field.
FERR_Write_Data_Error_DMA9: FERR_Write_Data_Error_DMA9
The DMA channel sets this bit indicating that the current transfer has encountered
an error while writing the destination data (e.g., no space available in DM). When
this bit has been set, the address of the failed descriptor is in the Channel Status
register.
FERR_Read_Data_Error_DMA8: FERR_Read_Data_Error_DMA8
The DMA channel sets this bit indicating that the current transfer has encountered
an error while accessing the source data. (e.g., starvation). When this bit has
been set, the address of the failed descriptor is in the Channel Status register.
FERR_DMA_Data_Parity Error_DMA7: FERR_DMA_Data_Parity
Error_DMA7
The DMA Engine has no internal parity checking and is hard-wired to 0.
FERR_Chipset_Data_Parity_Error_DMA6:
FERR_Chipset_Data_Parity_Error_DMA6
The DMA channel sets this bit indicating that the current transfer has encountered
a parity error reported by the chipset. When this bit has been set, the address of
the failed descriptor is in the Channel Status register.
In the case of Source data error, FERR*DMA8 is also set.
In the case of Destination data error, FERR*DMA9 is also set
FERR_CHANCMD_Error_DMA5: FERR_CHANCMD_Error_DMA5
The DMA channel sets this bit indicating that a write to the CHANCMD register
contained an invalid value (e.g., more than one command bit set).
®
®
5100 MCH Chipset does not detect unaffiliated errors
5100 MCH Chipset DMA Engine does not record/detect any soft errors.
Section 3.11.22.2
1
or has not been configured. This address will be
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
235