HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 7

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Contents—Intel
July 2009
Order Number: 318378-005US
3.10
3.11
3.9.2
3.9.3
3.9.4
3.9.5
3.9.6
3.9.7
3.9.8
3.9.9
3.9.10 Memory Interface Control ...................................................................... 213
3.9.11 Serial Presence Detect Registers ............................................................ 214
DMA Engine Configuration Registers .................................................................. 216
CB_BAR MMIO Registers .................................................................................. 217
3.11.1 PEXCMD: PCI Command Register ........................................................... 220
®
5100 MCH Chipset
3.9.2.1
3.9.2.2
3.9.2.3
3.9.2.4
3.9.3.1
3.9.3.2
3.9.3.3
3.9.3.4
3.9.3.5
3.9.3.6
3.9.3.7
3.9.4.1
3.9.4.2
3.9.4.3
3.9.5.1
3.9.5.2
3.9.5.3
3.9.6.1
3.9.6.2
3.9.6.3
3.9.6.4
3.9.6.5
3.9.6.6
3.9.6.7
3.9.6.8
3.9.6.9
3.9.6.10 NRECMEMB[1:0]: Non-Recoverable Memory Error Log Register B .. 205
3.9.6.11 REDMEMA[1:0]: Recoverable Memory Data Error Log Register A ... 206
3.9.6.12 REDMEMB[1:0]: Recoverable Memory Data Error Log Register B ... 206
3.9.6.13 RECMEMA[1:0]: Recoverable Memory Error Log Register A ........... 207
3.9.6.14 RECMEMB[1:0]: Recoverable Memory Error Log Register B........... 207
3.9.7.1
3.9.7.2
3.9.8.1
3.9.8.2
3.9.8.3
3.9.8.4
3.9.8.5
3.9.9.1
3.9.9.2
3.9.9.3
3.9.9.4
3.9.10.1 DSRETC[1:0]: DRAM Self-Refresh Extended Timing and Control .... 213
3.9.11.1 SPDDATA - Serial Presence Detect Status Register ...................... 214
3.9.11.2 SPDCMD: Serial Presence Detect Command Register ................... 214
Memory Throttling Control Registers ....................................................... 188
Memory Gearing Registers ..................................................................... 191
DRAM Timing Registers ......................................................................... 195
Memory Map Registers .......................................................................... 198
Memory Error Registers......................................................................... 199
Sparing Registers ................................................................................. 208
Memory RAS Registers .......................................................................... 209
Memory Control Debug Registers............................................................ 212
GBLACT: Global Activation Throttle Register ............................... 189
THRTSTS[1:0]: Throttling Status Register .................................. 189
THRTHIGH: Thermal Throttle High Register ................................ 190
THRTLOW: Thermal Throttle Low Register .................................. 191
DDRFRQ: DDR Frequency Ratio ................................................ 191
MEMTOHOSTGRCFG0: MEM to Host Gear Ratio Configuration 0 ..... 192
MEMTOHOSTGRCFG1: MEM to Host Gear Ratio Configuration 1 ..... 192
MEMNDGRCFG0: MEM Next Data Gear Ratio Configuration 0......... 193
MEMNDGRCFG1: MEM Next Data Gear Ratio Configuration 1......... 193
HOSTTOMEMGRCFG0: Host to MEM Gear Ratio Configuration 0 ..... 194
HOSTTOMEMGRCFG1: Host to MEM Gear Ratio Configuration 1 ..... 194
DRTA[1:0]: DRAM Timing Register A ......................................... 196
DRTB[1:0]: DDR Timing Register B ........................................... 197
DRPADCTL[1:0]: DRAM Pads Control Register............................. 197
TOLM - Top Of Low Memory ..................................................... 198
MIR[1:0]: Memory Interleave Range ......................................... 198
AMIR[1:0]: Adjusted Memory Interleave Range .......................... 199
FERR_NF_MEM: MC First Non Fatal Errors .................................. 200
NERR_NF_MEM: MC Next Non-Fatal Errors ................................. 200
EMASK_MEM: MC Error Mask Register ....................................... 201
ERR0_MEM: MC Error 0 Mask Register ....................................... 202
ERR1_MEM: MC Error 1 Mask Register ....................................... 203
ERR2_MEM: MEM Error 2 Mask Register ..................................... 203
MCERR_MEM: MEM MCERR Mask Register .................................. 204
VALIDLOG[1:0]: Valid Log Markers ........................................... 205
NRECMEMA[1:0]: Non-Recoverable Memory Error Log Register A .. 205
SPCPC[1:0]: Spare Copy Control .............................................. 208
SPCPS[1:0]: Spare Copy Status................................................ 208
RANKTHRESHOLD[1:0][5:0]: RANK Count Threshold ................... 209
CERRCNT[1:0]: Correctable Error Count .................................... 210
CERRCNT_EXT[1:0]: Correctable Error Count ............................. 210
BADRAM[1:0]: Bad DRAM Marker ............................................. 211
BADCNT[1:0]: Bad DRAM Counter............................................. 211
MEM[1:0]EINJMSK0: Memory Error Injection Mask0 Register ........ 212
MEM[1:0]EINJMSK1: Memory Error Injection Mask1 Register ........ 212
MEMEINJADDRMAT: Error Injection Address Match Register.......... 213
MEMEINJADDRMSK: Error Injection Address Mask Register........... 213
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
7