HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 16

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Intel
Datasheet
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5100 Memory Controller Hub Chipset
PCI Express* Port 6 Signals .......................................................................................50
PCI Express* Port 7 Signals .......................................................................................51
PCI Express* Graphics Port Signals .............................................................................51
SMBus Interfaces Signals ..........................................................................................52
Extended Debug Port (XDP) Signals ............................................................................53
JTAG Bus Signals......................................................................................................53
Clocks, Reset and Miscellaneous Signals ......................................................................54
Power and Ground Signals .........................................................................................55
Power Up and Hard Reset Timings ..............................................................................62
Critical Intel
Signals Used as Straps ..............................................................................................64
Register Attributes Summary Table .............................................................................65
Configuration Address Bit Mapping ..............................................................................71
Functions Specially Handled by Intel
Access to “Non-Existent” Register Bits .........................................................................73
I/O Address: CF8h ....................................................................................................74
I/O Address: CFCh....................................................................................................74
Mapping for Fixed Memory Mapped Registers ...............................................................74
Device 0, Function 0: PCI Express* PCI Space ..............................................................76
Device 0, Function 0: PCI Express* Extended Registers .................................................77
Device 2-3, Function 0: PCI Express* PCI Space ...........................................................78
Device 2-3, Function 0: PCI Express* Extended Registers ..............................................79
Device 4, Function 0: PCI Express* PCI Space ..............................................................80
Device 4, Function 0: PCI Express* Extended Registers .................................................81
Device 5-7, Function 0: PCI Express* PCI Space ...........................................................82
Device 5-7, Function 0: PCI Express* Extended Registers ..............................................83
Device 16, Function 0: Processor Bus, Boot, and Interrupt .............................................84
Device 16, Function 0: Processor Bus 0 Error Registers..................................................85
Device 16, Function 0: Processor Bus 1 Error Registers..................................................86
Device 16, Function 1: Memory Branch Map, Control, Errors...........................................87
Device 16, Function 1: Memory Gearing Registers.........................................................88
Device 16, Function 1: Memory DFx Registers ..............................................................89
Device 16, Function 2: RAS........................................................................................90
Device 21, 22, Function 0: DIMM Map, Control, RAS......................................................91
Device 21, 22, Function 0: Memory Map, Control, Errors................................................92
Address Mapping Registers ........................................................................................97
XTPR Index............................................................................................................ 110
Accessibility of the Intel
Intel
Handling ............................................................................................................... 120
GIO Port Mode Selection.......................................................................................... 127
IV Handling and Processing by Intel
Maximum Link Width Default Value for Different PCI Express* Ports .............................. 146
Negotiated Link Width For Different PCI Express* Ports After Training ........................... 148
Timing Characteristics of ERRPER ............................................................................. 186
Global Activation Throttling as Function of Global Activation Throttling Limit (GBLACTM)
Register Fields ....................................................................................................... 189
MEM to Host Gear Ratio Mux for MEMTOHOSTGRCFG0 ................................................. 192
MEM to Host Gear Ratio Mux for MEMTOHOSTGRCFG1 ................................................. 193
MEM to Host Gear Ratio Mux for MEMNDGRCFG0 ........................................................ 193
MEM to Host Gear Ratio Mux for MEMNDGRCFG1 ........................................................ 194
Host to MEM Gear Ratio Mux Select........................................................................... 194
Host to MEM Gear Ratio Mux Select........................................................................... 195
Interleaving of Address Is Governed by MIR[i] if ......................................................... 199
ECC Locator Mapping Information ............................................................................. 206
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5100 Memory Controller Hub Chipset PEXSTS and SECSTS Master/Data Parity Error RAS
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5100 Memory Controller Hub Chipset Initialization Timings.........................63
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5100 Memory Controller Hub Chipset PCI Express* Device....... 111
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5100 Memory Controller Hub Chipset.................... 139
5100 Memory Controller Hub Chipset .....................72
Intel
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5100 MCH Chipset—Contents
Order Number: 318378-005US
July 2009