HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 188

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.9.1.7
3.9.2
Intel
Datasheet
188
®
5100 Memory Controller Hub Chipset
DMIR[1:0][4:0] - DIMM Interleave Range
These registers define rank participation in various DIMM interleaves.
Each register defines a range. If the Memory (M) address falls in the range defined by
an adjacent pair of DMIR.LIMIT’s, the rank fields in the upper DMIR define the number
and interleave position of ranks’ way participation. Matching addresses participate in
the corresponding ways. The combination of two equal ranks with three unequal ranks
is illegal.
When a DMIR is programmed for a 2-way interleave, RANK0/RANK2 should be with the
same rank number and RANK1/RANK3 should be another rank number.
This register must not be modified while servicing memory requests.
Memory Throttling Control Registers
The Intel
activates to a given rank are monitored and possibly limited as required. There are two
levels of throttling, low (normal operation) and high (activations throttling triggered),
and the levels of activity permitted at both these levels are selected by the BIOS.
Device:
Function:
Offset:
Device:
Function:
Offset:
31:27
26:16
14:12
1:0
Bit
10:8
6:4
2:0
Bit
15
11
7
3
Attr
RW
®
Attr
RW
RW
RW
RW
RW
RV
RV
RV
RV
RV
5100 MCH Chipset employs activation based throttling where the number of
22, 21
0
1B2h, 1B0h, 15Ah, 158h, 156h, 154h
22, 21
0
16Ch, 168h, 164h, 160h, 15Ch
Default
00
Default
000h
00h
000
000
000
000
0h
0
0
0
NUMCOL: Technology - Number of Columns
Defines the number of columns within these DIMMs
“00”
“01”
“10”
“11”
Reserved
LIMIT
This field defines the highest address in the range. Memory requests
participate in this DMIR range if LIMIT[i] > M[37:28] >= LIMIT[i-1]. For i = 0,
LIMIT[i-1]=0.
Reserved
RANK3
Defines which rank participates in WAY3. Only bits [1:0] are used.
Reserved
RANK2
Defines which rank participates in WAY2. Only bits [1:0] are used.
Reserved
RANK1
Defines which rank participates in WAY1. Only bits [1:0] are used.
Reserved
RANK0
Defines which rank participates in WAY0. Only bits [1:0] are used.
= 1,024, 10 columns
= 2,048, 11 columns
= 4,096, 12 columns (Not Supported)
= Reserved
Intel
Description
®
Description
5100 MCH Chipset—Register Description
Order Number: 318378-005US
July 2009