HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 332

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 103.
Table 104.
Table 105.
Intel
Datasheet
332
®
5100 Memory Controller Hub Chipset
Incoming PCI Express* Completions
1. Outbound Memory writes are posted and have no completions
Outgoing PCI Express* Requests
Outgoing PCI Express* Completions
PCI Express*
Completions
for Outbound
Writes
Completions
for Outbound
Reads
PCI Express*
Outbound
Write
Requests
Outbound
Read Requests
Outbound
Messages
PCI Express*
Inbound Read
Completions
Transaction
Transaction
Transaction
I/O or Configuration
Memory, I/O or Configuration
Memory
I/O
Configuration
Memory
I/O
Configuration
EOI
(Intel-specific)
Lock/Unlock
PM_TURN_OFF
PM_REQUEST_ACK
(DLLP)
Attention_Indicator_On
Attention_Indicator_Off
Attention_Indicator_Blink
Power_Indicator_On
Power_Indicator_Off
Power_Indicator_Blink
CB Query Response
Memory
I/O
Address Space or Message
Address Space or Message
Address Space or Message
1
Forward to the processor bus, PCI Express* or ESI from
which the request originated.
Forward to the processor bus, PCI Express* or ESI from
which the request originated.
Processor bus or peer memory-mapped I/O write targeting
PCI Express* device.
Processor or peer configuration write targeting PCI Express*
device.
Processor or peer memory-mapped I/O read targeting PCI
Express* device.
Processor or peer I/O read targeting PCI Express* device.
Processor or peer configuration read targeting PCI Express*
device.
End-of-interrupt cycle received on processor bus, Intel
5100 MCH Chipset broadcasts this message to all active PCI
Express* ports. Devices supporting edge triggered interrupts
will ignore this cycle.
When a locked read or write transaction was previously
issued to a PCI bridge, “Unlock” releases the PCI lock.
PEXGCTRL.PME_TURN_OFF bit was set. This message is
broadcast to all enabled PCI Express* ports.
Received PM_ENTER_L1 and PM_ENTER_L23. This message
is continuously issued until link is idle.
PEXSLOTCTRL.“Attention Indicator Control” has been set to
On.
PEXSLOTCTRL.“Attention Indicator Control” has been set to
Off.
PEXSLOTCTRL.“Attention Indicator Control” has been set to
Blink.
PEXSLOTCTRL.“Power Indicator Control” has been set to On.
PEXSLOTCTRL.“Power Indicator Control” has been set to Off.
PEXSLOTCTRL.“Power Indicator Control” has been set to
Blink.
This message is sent back by the Intel
in response to the DMA Engine query and contains pertinent
information on DMA Engine version, BAR offset etc.
Response for an inbound read to main memory or a peer I/O
device.
Response for an inbound read to a peer I/O device.
Processor legacy I/O write targeting PCI Express* device.
Intel
®
Intel
5100 Memory Controller Hub Chipset Response
®
5100 MCH Chipset—Functional Description
Reason for Issue
Reason for Issue
Order Number: 318378-005US
®
5100 MCH Chipset
July 2009
®