HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 161

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.12.7
July 2009
Order Number: 318378-005US
UNCERRSEV[7:2] - Uncorrectable Error Severity
This register indicates the severity of the uncorrectable errors. An error is reported as
fatal when the corresponding error bit in the severity register is set. If the bit is
cleared, the corresponding error is considered non-fatal. If an error is recorded in the
UNCERRSTS register, the appropriate bit of UNCERRSEV determines if the error gets
reflected as a device fatal or nonfatal error in the PEX_FAT_FERR, PEX_NF_COR_FERR,
PEX_FAT_NERR, PEX_NF_COR_NERR registers.
Device:
Function:
Offset:
Device:
Function:
Offset:
31:21
11:6
3:1
3:1
Bit
Bit
20
19
18
17
16
15
14
13
12
5
4
0
5
4
0
®
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
5100 MCH Chipset
Attr
Attr
RV
RV
RV
RV
RV
0
0
10Ch
7-2
0
10Ch
Default
Default
000
000
0h
0h
1
1
1
0
0
1
1
0
0
0
1
0
1
1
1
IO19Severity: Surprise Link-down Severity
IO0Severity: Data Link Protocol Error Severity
(See Figure 3-17 in PCI Express* Base Specification, Rev. 1.0a)
Reserved
IO3Severity:Training Error Severity
This field should not be used for setting Training error severity due to a
recent PCI Express* Base Specification, Rev. 1.0a Errata Dec 2003 to
remove training error. Hardware behavior is undefined.
Reserved
IO2Severity: Received an Unsupported Request
Reserved
IO9Severity: Malformed TLP Severity
IO10Severity: Receiver Buffer Overflow Severity
IO8Severity: Unexpected Completion Severity
IO7Severity: Completer Abort Status
IO6Severity: Completion Timeout Severity
IO5Severity: Flow Control Protocol Error Severity
IO4Severity: Poisoned TLP Severity
Reserved
IO19Severity: Surprise Link-down Severity
IO0Severity: Data Link Protocol Error Severity
(See Figure 3-17 in PCI Express* Base Specification, Rev. 1.0a)
Reserved
IO3Severity:Training Error Severity
This field should not be used for setting Training error severity due to a
recent PCI Express* Base Specification, Rev. 1.0a Errata Dec 2003 to
remove training error. Hardware behavior is undefined.
Description
Intel
Description
®
5100 Memory Controller Hub Chipset
Datasheet
161