HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 250

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.11.23.9
Intel
Datasheet
250
®
5100 Memory Controller Hub Chipset
CHANERRMSK[3:0]: Channel Error Mask Register
The Channel Error Mask Register provides selective control to mask errors from before
being signaled. They are still recorded in the CHANERR, FERR/NERR_CHANERR log
registers irrespective of the value in this register. If one of the bits in the CHANERRMSK
register is set, then that specific error does not cause interrupt signaling.
Offset:
3
2
1
0
Offset:
31:16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
Bit
RWCST
RWCST
RWCST
RWCST
RV
RO
RO
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
Attr
Attr
228h, 1A8h, 128h, A8h
22Ch, 1ACh, 12Ch, ACh
0
0
0
0
0h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Default
Default
Desc_err: Descriptor Error
The DMA channel sets this bit indicating that the current descriptor has
encountered an error when executing a DMA descriptor that is not otherwise
related to other error bits, e.g., an illegal next descriptor address flagged by the
system Address decoder, which the DMA Engine encounters in the current
descriptor after having successfully completed the data transfer for the current
descriptor including any associated completions/interrupts. When this bit has
been set and the channel returns to the Halted state, the address of the failed
descriptor is in the Channel Status register.
Nxt_desc_addr_err: Next Descriptor Address Error
The DMA channel sets this bit indicating that the current descriptor has an illegal
next descriptor address (e.g., >40-bits) including next descriptor alignment error
(not on a 64-byte boundary). This error could be flagged when the data for the
current descriptor is fetched and its constituent fields are checked.
DMA_xfer_daddr_err: DMA Transfer Destination Address Error
The DMA channel sets this bit indicating that the current descriptor has an illegal
destination address. When this bit has been set, the address of the failed
descriptor when the channel returns to the Halted state, is recorded in the
Channel Status register.
DMA_trans_saddr_err: DMA Transfer Source Address Error
The DMA channel sets this bit indicating that the current descriptor has an illegal
source address. When this bit has been set, the address of the failed descriptor
when the channel returns to the Halted state, is recorded in the Channel Status
register.
Reserved
Unaffil_err_Msk: Unaffiliated Error Mask
Soft_err_Msk: Soft Error Mask
int_cfg_err_Msk: Interrupt Configuration Error Mask
Cmp_addr_err_Msk: Completion Address Error Mask
Desc_len_err_Msk: Descriptor Length Error Mask
Desc_ctrl_err_Msk: Descriptor Control Error Mask
Wr_data_err_Msk: Write Data Error Mask
Rd_data_err_Msk: Read Data Error Mask
DMA_data_par_err_Mskr: DMA Data Parity Error Mask
Cdata_par_err_Msk: Chipset Data Parity Error Mask
Chancmd_err_Msk: CHANCMD Error Mask
Chn_addr_val_err_Msk: Chain Address Value Error Mask
Desc_err_Msk: Descriptor Error Mask
Nxt_desc_addr_err_Msk: Next Descriptor Address Error Mask
DMA_xfrer_daddr_err_Msk: DMA Transfer Destination Address Error Mask
Intel
Description
Description
®
5100 MCH Chipset—Register Description
Order Number: 318378-005US
July 2009