HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 311

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
Figure 27.
5.13.3
July 2009
Order Number: 318378-005US
PCI Express* High Performance x16 Port
Supported Length Width Port Partitioning
To establish a connection between PCI Express* endpoints, they both participate in a
sequence of steps known as training. This sequence will establish the operational width
of the link as well as adjust skews of the various lanes within a link so that the data
sample points can correctly take a data sample off of the link. In the case of a x8 port,
the x4 link pairs will first attempt to train independently, and will collapse to a single
link at the x8 width upon detection of a single device returning link ID information
upstream. Once the number of links has been established, they will negotiate to train
at the highest common width, and will step down in its supported link widths in order to
succeed in training. The ultimate result may be that the link has trained as a x1 link.
Although the bandwidth of this link size is substantially lower than a x8 link or x4 link,
it will allow communication between the two devices. Software will then be able to
interrogate the device at the other end of the link to determine why it failed to train at
a higher width.
This autonomous capability can be overridden by the values sampled on the
PEWIDTH[3:0] pins.
CPCI Configuration in Intel® 5100 Memory Controller Hub Chipset”
PEWIDTH strapping options for various link widths in the PCI Express* ports in the
MCH.
®
5100 MCH Chipset
P o rt 4
H ig h P e rfo rm a n ce G ra p h ic s P o rt
Table 95, “PCI Express* Link Width Strapping Options for Port
P C I E x p re s s * c lu s te r (IO U 1 )
P o rt 5
T ra n s a c tio n
P h y s ic a l
L in k
P o r t 6
Intel
®
5100 Memory Controller Hub Chipset
P o r t 7
illustrates the
Datasheet
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