HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 386

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

7.0
7.1
7.1.1
Table 137.
Intel
Datasheet
386
®
5100 Memory Controller Hub Chipset
Testability
JTAG Port
Each component in the Intel
slave which complies with the IEEE 1149.1 (JTAG) test architecture standard. Basic
functionality of the 1149.1- compatible test logic is described here-in, for details
reference the IEEE 1149.1 standard.
TAP Signals
The TAP logic is accessed serially through five dedicated pins on each component as
shown in
TAP Signal Definitions
TMS, TDI and TDO operate synchronously with TCK (which is independent of all other
clocks). TRST# is an asynchronous reset input signal. This 5-pin interface operates as
defined in the 1149.1 specification. A simplified block diagram of the TAP used in Intel
5100 MCH Chipset components is shown in
Diagram.”
TCK
TMS
TDI
TDO
TRST#
Table 137, “TAP Signal Definitions.”
TAP Clock input
Test Mode Select. Controls the TAP finite state machine.
Test Data Input. The serial input for test instructions and data.
Test Data Output. The serial output for the test data.
Test Reset input.
®
5100 MCH Chipset includes a Test Access Port (TAP)
Figure 55, “Simplified TAP Controller Block
Intel
®
5100 MCH Chipset—Testability
Order Number: 318378-005US
July 2009
®