HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 31

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Introduction—Intel
July 2009
Order Number: 318378-005US
The Intel
embedded application systems based on the Dual-Core Intel
series, Quad-Core Intel
processor 5200 series and Quad-Core Intel
Core™2 Duo Processor T9400 for UP designs. The Intel
two processors on dual independent point to point system buses operating at 266 MHz
(1066 MT/s) or 333 MHz (1333 MT/s); the peak bandwidth of the two processor busses
is respectively, 17 GB/s and 21 GB/s for outbound and 8 GB/s and 10 GB/s for inbound
accesses. The MCH supports 36-bit addressability with a total of 32 GB or 48 GB
depending upon mode.
The Quad-Core Intel
Intel
L2 cache and a 266 MHz (1066 MT/s) system bus. The Dual-Core Intel
processor 5100 series (65 nm process) and Dual-Core Intel
series (45 nm process) have 4 MB and 6 MB shared L2 cache, respectively, and a 333
MHz (1333 MT/s) system bus. The Intel
process) has 6 MB shared L2 cache and a 266 MHz (1066 MT/s) system bus.
The MCH provides two channels of registered ECC memory DIMMs. In 32 GB Mode,
each channel can support up to four ranks of DDR2 memory for a maximum physical
memory configuration of 32 GB. The four ranks are recommended to be configured
across two to three DIMMs. In 48 GB mode, each channel can support up to six ranks of
DDR2 memory for a maximum physical memory configuration of 48 GB. The six ranks
per channel are required to be configured across up to three DIMMs with up to four
ranks per DIMM. For currently supported DIMM configurations, see the Quad-Core and
Dual-Core Intel
Hub Chipset for Communications, Embedded, and Storage Applications – Platform
Design Guide or Intel
Memory Controller Hub Chipset for Communications and Embedded Applications –
Platform Design Guide. The read bandwidth for each channel is 5.3 GB/s for DDR2 667
memory and 4.25 GB/s for DDR2 533. This provides a maximum bandwidth of 10.6
GB/s for two DDR2 channels.
The MCH offers six PCI Express* x4 ports compliant to PCI Express* Base Specification,
Rev. 1.0a. Configured appropriately, the ports can be combined to form x4, x8 or x16
ports.
The ICH9R is an I/O controller hub supporting various I/O interfaces including six PCI
Express* x1 ports, Serial ATA host controllers supporting up to six SATA ports at a
speed of 3 Gb/s, twelve external USB 2.0 ports with port disable capability, a System
Management Bus interface (SMBus), a Serial Peripheral Interface (SPI) and a Low
Pincount bus (LPC) for BIOS and firmware storage. Additionally, the ICH9R contains a
PCI Controller supporting up to four Bus Masters (PCI Local Bus Specification, Rev. 2.3
compliant), an integrated 10/100/1000 LAN controller and a dedicated ESI port for
communication with the MCH. The ICH9R component provides the data buffering and
arbitration required to ensure that system interfaces operate efficiently and provide the
bandwidth necessary to enable the system to obtain peak performance.
The ICH9R component is ACPI compliant and can support the Full-on, Stop Grant,
Suspend to RAM, Suspend to Disk, and Soft-Off power management states. Through
the use of the integrated LAN functions, the ICH9R also supports Alert Standard Format
for remote management.
®
5100 MCH Chipset
®
Xeon
®
5100 MCH Chipset is designed for server, communications, storage, and
®
processor 5400 series (45 nm process) have 2x4 MB and 2x6 MB shared
®
Xeon
®
®
®
Xeon
®
Core™2 Duo Processors T9400 and SL9400 and Intel
Processor 5000 Sequence with Intel
Xeon
®
processor 5300 series (65 nm process) and Quad-Core
®
processor 5300 series, Dual-Core Intel
®
Core™2 Duo Processor T9400 (45 nm
®
Xeon
®
processor 5400 series and Intel
Intel
®
®
5100 MCH Chipset supports
5100 Memory Controller Hub Chipset
®
®
®
Xeon
5100 Memory Controller
Xeon
®
®
processor 5200
processor 5100
®
®
Xeon
Xeon
®
®
®
5100
Datasheet
®
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