HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 331

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.17.2
Table 102.
July 2009
Order Number: 318378-005US
Supported PCI Express* Transactions
Table 102, “Incoming PCI Express* Requests”
Intel
interface. Similarly,
transactions to be expected by an attached PCI Express* component. Refer to the PCI
Express* Base Specification, Rev. 1.0a for the specific protocol requirements of this
interface.
Incoming PCI Express* Requests
PCI Express*
Inbound Write
Requests
Inbound Read
Requests
Inbound
Message
Transaction
®
5100 MCH Chipset which are expected to be received from the PCI Express*
®
5100 MCH Chipset
Memory
I/O
Memory
I/O
Assert_INTA
Deassert_INTA
Assert_INTB
Deassert_INTB
Assert_INTC
Deassert_INTC
Assert_INTD
Deassert_INTD
ERR_COR
ERR_UNC
ERR_FATAL
PM_PME
PM_TO_ACK
PM_ENTER_L1, PM_ENTER_L23
(DLLP)
ATTENTION_BUTTON_PRESSED
Assert_GPE
Deassert_GPE
FENCE_MSG
CB Query
Others
Address Space or Message
Table 104, “Outgoing PCI Express* Requests”
Forward to Main Memory or PCI Express* or ESI port
depending on address.
Forward to peer PCI Express* or ESI port
Forward to Main Memory, or PCI Express* or ESI
Forward to peer PCI Express* or ESI Interface port
Inband interrupt assertion/deassertion emulating PCI
interrupts.
Inband interrupt assertion/deassertion emulating PCI
interrupts.
Inband interrupt assertion/deassertion emulating PCI
interrupts.
Inband interrupt assertion/deassertion emulating PCI
interrupts.
Propagate as an interrupt to system.
Propagate as an interrupt to system.
Propagate as an interrupt to system.
Propagate as a general purpose event to the system via the
PME_OUT pin.
Terminate the PME_Turn_OFF message issued from the
originating PCI Express* port
These messages are issued by downstream components that
indicate their entry into L1 or L2/L3 states. The Intel
MCH Chipset must block subsequent TLP issue and wait for
all pending TLPs to Ack. Then, send PM_REQUEST_ACK.
Terminate the message and set the PEXSLTSTS.“Attention
Button Pressed”. If PEXCTRL.“Attention Button Pressed
Enable”and “Hot-Plug Interrupt Enable” bits are set, send
MSI, Assert_HPGPE, or Assert_INTx on the ESI.
Send the received “Assert_GPE” message at the PCI
Express* port to the ESI port as a virtual wire using a wired-
OR approach.
Note:
Send the received “Deassert_GPE” message at the PCI
Express* port to the ESI port as a virtual wire using a wired-
OR approach.
Note:
This message is used to provide ordering between different
streams in the given PCI Express* port
This message is sent by the device to request information on
the DMA Engine BAR and per port offset for configuration.
Set IO2 error (unsupported request), drop transaction
(master abort) and return credit.
Intel
®
5100 Memory Controller Hub Chipset Response
lists all the transactions supported by the
This is an Intel vendor-specific message.
This is an Intel vendor-specific message.
Intel
®
5100 Memory Controller Hub Chipset
lists all the
Datasheet
®
5100
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