HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 130

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Intel
Datasheet
130
®
5100 Memory Controller Hub Chipset
Device:
Function:
Offset:
20:13
9:2
Bit
21
12
11
10
9
8
7
Attr
RW
RW
RW
RW
RW
RW
RV
RV
RV
7-2,0
0
48h
Default
21h
0h
0
0
0
0
0
0
1
MALTLP_EN:
1: Check for certain malformed TLP types.
0: Do not check for certain malformed TLP types.
Suggested value: 1
When this bit is set, it enables the following conditions to mark a packet
as malformed:
Reserved
Max_rdcmp_lmt_EN: Maximum Read completion combining limit
Enable
1: Up to 256 bytes return and COALESCE_EN = 1.
0: Up to 128 bytes return if COALESCE_EN = 1
Note:
COALESCE_FORCE: Force coalescing of accesses.
When 1, forces the Intel
data before sending the transaction as opposed to forwarding as much as
possible.
0: Normal operation
1: wait to coalesce data
Note:
COALESCE_EN: Read completion coalescing enable
When 1, enables read return of >64 bytes.
1: Returns of >64 bytes enabled. (See Max_rdcmp_lmt_EN above).
0: Returns are 64 bytes or less.
Note:
Reserved
PMEGPEEN: PME GPE Enable
1: Enables Assert_PMEGPE (Deassert_PMEGPE) messages to be sent
over the ESI from the root complex for PM interrupts.
0: Disables Assert_PMEGPE (Deassert_PMEGPE) messages for PM events
to the root complex.
This has an overriding effect to generate ACPI PM interrupts over
traditional interrupts (MSI/INTx).
HPGPEEN: PCI Hot Plug* GPE Enable
1: Enables Assert_HPGPE (Deassert_HPGPE) messages to be sent from
the root complex for PCI Hot Plug* events.
0: Disables Assert_HPGPE (Deassert_HPGPE) messages for PCI Hot Plug*
events from the root complex.
This has an overriding effect to generate ACPI HP events over traditional
interrupts.
Reserved
• 4 DW header MEM_RD or MEM_WR and the address is less than 32
• Byte enable check for mem/io/cfg requests. Length > 1 DW and
• IO{rd,wr}/cfg{rd,wr}{0,1} and (traffic class != 0 or attributes != 0
• A configuration retry completion response (CRS) received for a non-
bits (address[39:32] = 0)
(first dword byte enables = 0 or last dword byte enables = 0) Length
= 1 DW and last dword byte enables != 0
or length != 1)
cfg outbound request
It is recommended that this field should not be set to 1 (256
bytes completion combining).
It is recommended that COALESCE_FORCE should not be set to
‘1.’
For optimal read completion combining, this field should be set
to ‘1’ along with Max_rdcmp_lmt_EN as ‘0’ for 128 bytes
completion combining
Intel
®
5100 MCH Chipset to wait for all coalescable
®
5100 MCH Chipset—Register Description
Description
Order Number: 318378-005US
July 2009