HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 363

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
Table 116.
5.20.10.1
July 2009
Order Number: 318378-005US
1. The Intel
®
The Intel
through pins GPIOSMBCLK, and GPIOSMBDATA, for PCI Express* ports that connect to
a variable number of serial to parallel I/O ports such as the Phillips* PCA9555
Extender. The Intel
mapped as per
two 8-bit ports that can be configured as inputs or outputs. The Intel
Chipset has a crossbar which associates each PCI Hot Plug* Unit slots with one of these
8-bit ports. The mapping is defined by a Virtual Pin Port register field, PEXCTRL.VPP, for
each of the PCI Hot Plug* Unit slots. The VPP register holds the SMBus address and
port number of the I/O Port associated with the PCI Hot Plug* Unit. A[2:0] pins on each
I/O Extender (i.e., Phillips* PCA9555 or compatible components) connected to the
Intel
Hot Plug* signals are mapped to pins on the VPP.
I/O Port Registers in I/O Extender Supported by
Intel
Operation
When the Intel
a reset, the Intel
connected to it, what their addresses are, nor what PCI Express* ports are PCI Hot
Plug*-able. The Intel
SMBus until a PCI Hot Plug* Capable bit is set.
For a PCI Express* slot, an additional DIS_VPP bit is used to differentiate card or
module PCI Hot Plug* support, DIS_VPP bit needs to be set to 0 to enable PCI Hot
Plug* support for PCI Express* card slot.
When BIOS sets a PCI Hot Plug* Capable bit (PEXSLOTCAP.HPC and PEXCTRL.DIS_VPP
for PCI Express*), the Intel
Direction and Voltage Logic Level configuration as per
Express* which do not have the PCI Hot Plug* capable bit set are invalid. Additionally,
if the DIS_VPP bit is set to 1, then the corresponding VPP register is invalid for the PCI
Express* slot. This is intended for PCI Express* module PCI Hot Plug* which no VPP
support is required. The I/O Extender’s Polarity is left at its default value and never
written, but the direction and voltage logic levels are written using the addresses
defined in
When the Intel
register reads and output register writes to all valid VPPs. This sequence repeats
indefinitely until a new PCI Hot Plug* capability bit is set. To minimize the completion
time of this sequence and minimize complexity, both ports are always read or written.
5100 MCH Chipset VPP supports Phillips* PCA9555 or compatible I/O Extender only.
Register
®
®
5100 MCH Chipset must strapped uniquely.
5100 Memory Controller Hub Chipset
0
1
2
3
4
5
6
7
®
Table
®
5100 MCH Chipset masters a 100 kHz PCI Hot Plug* SMBus interface
5100 MCH Chipset
®
®
Table
117.
5100 MCH Chipset comes out of reset, the I/O ports are inactive. After
®
5100 MCH Chipset is not doing a direction write, it performs input
®
5100 MCH Chipset is not aware of how many I/O Ports are
Polarity Inversion Port 0
Polarity Inversion Port 1
®
5100 MCH Chipset only supports SMBus devices with registers
116. These I/O Extender components have 16 I/Os, divided into
Configuration Port 0
Configuration Port 1
5100 MCH Chipset does not master any commands on the
Output Port 0
Output Port 1
Input Port 0
Input Port 1
Name
®
5100 MCH Chipset initializes the associated VPP with
Not written by Intel
Table 117
Intel
Continuously Writes Output Values
Continuously Reads Input Values
Intel
Direction set as per
Table
®
®
5100 MCH Chipset Usage
5100 Memory Controller Hub Chipset
117. VPP registers for PCI
defines how the eight PCI
®
5100 MCH Chipset
®
Table 117
5100 MCH
1
Datasheet
I/O
363