HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 42

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 6.
Intel
Datasheet
42
®
5100 Memory Controller Hub Chipset
Processor Front Side Bus 1 Signals (Sheet 3 of 4)
FSB1DBI[3:0]#
FSB1DBSY#
FSB1DEFER#
FSB1DP[3:0]#
FSB1DRDY#
FSB1DSTBP[3:0]#
FSB1DSTBN[3:0]#
FSB1HIT#
FSB1HITM#
Signal Name
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
Type
Processor 1 Dynamic Data Bus Inversion:
FSB1DBI[3:0]# are source synchronous and indicate the polarity of the
FSB1D[63:0]# signals. The FSB1DBI[3:0]# signals are activated when the data
on the data bus is inverted. If more than half the data bits, within, within a 16-
bit group, would have been asserted electronically low, the bus agent may
invert the data bus signals for that particular sub-phase for that 16-bit group.
The below table shows the signal relationships.
Processor 1 Data Bus Busy:
FSB1DBSY# is asserted by the agent responsible for driving data on the
processor FSB to indicate that the data bus is in use. The data bus is released
after FSB1DBSY# is deasserted. This signal is used by the data bus owner to
hold the data bus for transfers requiring more than one cycle.
Processor 1 Data Bus Defer:
FSB1DEFER# is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Defer indicates that the MCH will terminate the
transaction currently being snooped with either a deferred response or with a
retry response.
Processor 1 Data Bus Parity:
FSB1DP[3:0]# provide parity protection for the FSB1D[63:0]# signals. They
are driven by the agent responsible for driving the FSB1D[63:0]# signals.
Processor 1 Data Ready:
FSB1DRDY# is asserted by the data driver on each data transfer, indicating
valid data on the data bus. FSB1DRDY# may be deasserted to insert idle clocks.
FSB1DRDY# is asserted for each cycle that data is transferred.
Processor 1 Differential Host Data Strobes:
The differential source synchronous strobes used to transfer FSB1D[63:0]# and
FSB1DBI[3:0]# at the 4x transfer rate.
Processor 1 Cache Hit:
FSB1HIT# along with FSB1HITM# convey transaction snoop operation results.
Any FSB agent may assert both FSB1HIT# and FSB1HITM# together to indicate
that it requires a snoop stall to extend the snoop window. The stall an be
continued by reasserting FSB1HIT# and FSB1HITM# together. The FSB1HIT#
signal indicates that a caching agent holds an unmodified version of the
requested line.
Processor 1 Cache Hit Modified:
FSB1HITM# along with FSB1HIT# convey transaction snoop operation results.
Any FSB agent may assert both FSB1HITM# and FSB1HIT# together to indicate
that it requires a snoop stall to extend the snoop window. The stall an be
continued by reasserting FSB1HITM# and FSB1HIT# together. The FSB1HITM#
signal indicates that a caching agent holds a modified version of the requested
line.
Bus Inversion Signal
FSB1D[31:16]#
FSB1D[47:32]#
FSB1D[63:48]#
FSB1D[15:0]#
Data Group
FSB1DBI[0]#
FSB1DBI[1]#
FSB1DBI[2]#
FSB1DBI[3]#
FSB1DSTB{P/N}[0]#
FSB1DSTB{P/N}[1]#
FSB1DSTB{P/N}[2]#
FSB1DSTB{P/N}[3]#
Data Strobe
FSB1D[31:16]#
FSB1D[47:32]#
FSB1D[63:48]#
FSB1D[15:0]#
Data Group
Intel
Description
®
5100 MCH Chipset—Signal Description
Bus Inversion Signal
Order Number: 318378-005US
FSB1DBI[0]#
FSB1DBI[1]#
FSB1DBI[2]#
FSB1DBI[3]#
July 2009