HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 227

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.11.9.2
3.11.10
July 2009
Order Number: 318378-005US
PMCSR - Power Management Control and Status Register
This register provides status and control information for PM events in the PCI Express*
port of the DMA Engine Device.
MSICAPID - Message Signaled Interrupt Capability ID Register
Device:
Function:
Offset:
Device:
Function:
Offset:
7:0
31:24
21:16
14:13
12:9
Bit
7:2
1:0
Bit
23
22
15
8
RO
Attr
®
RWCST
RWST
Attr
5100 MCH Chipset
RW
RO
RO
RO
RO
RO
RV
RV
8
0
54h
8
0
58h
05h
Default
Default
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
CAPID: MSI Capability ID
This code denotes the standard MSI capability assigned by PCI-SIG
Data: Data
Data read out based on data select (DSEL). Refer to section 3.2.6 of PCI
Bus Power Management Interface Specification, revision 1.1, for details.
This is not implemented in the e Power Management capability for the
Intel
BPCCEN: Bus Power/Clock Control Enable
This field is hardwired to 0h.
B2B3S: B2/B3 Support
This field is hardwired to 0h.
Reserved.
PMESTS: PME Status
This PME Status is a sticky bit. When set, the device generates a PME
internally independent of the PMEEN bit defined below. Software clears this
bit by writing a ‘1’.
As an integrated device within the root complex, the Intel
Chipset will never set this bit, because it never generates a PME internally
independent of the PMEEN bit.
DSCL: Data Scale
This 2-bit field indicates the scaling factor to be used while interpreting the
“data_scale” field.
DSEL: Data Select
This 4-bit field is used to select which data is to reported through the
“data” and the “Data Scale” fields.
PMEEN: PME Enable
This field is a sticky bit and when set enables PMEs generated internally to
appear at the ICH9R through the “Assert(Deassert)_PMEGPE”message.
This has no effect on the Intel
generate PME events internally.
Reserved.
PS: Power State
This 2-bit field is used to determine the current power state of the function
and to set a new power state as well.
00: D0
01: D1 (reserved)
10: D2 (reserved)
11: D3_hot
®
5100 MCH Chipset and is hardwired to 0h.
Description
®
Description
Intel
5100 MCH Chipset since it does not
®
5100 Memory Controller Hub Chipset
®
5100 MCH
Datasheet
227