HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 362

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.20.10
Note:
Figure 53.
Intel
Datasheet
362
1. This does not include the ESI (port 0) which is not PCI Hot Plug*-able.
®
5100 Memory Controller Hub Chipset
The compatible set of PCI Hot Plug* registers may be accessed via memory-mapped
transactions, or via the Intel
information on the PCI Hot Plug* register set, refer to the
Configuration Space Maps.”
Virtual Pin Ports
Shown in the
maximum number of PCI Express* card slots that could be supported for PCI Hot Plug*
operations. In this VPP usage model, 16 slots (max) are shown in
the Intel
only support up to six PCI Express* slots
Accordingly, the Intel
process six PCI Hot Plug* slots.
Port 0, the ESI slot, is not PCI Hot Plug*-able.
PCI Hot Plug*/VPP Block Diagram
ICH9R
®
5100 MCH Chipset only supports six PCI Express* ports and, therefore, can
Button
Slot 0
LED
Figure 53
I/O extender 0
A2 A1 A0
Button
®
Slot 1
LED
5100 MCH Chipset PCI Express* virtual pin port will only
is a high level block diagram of virtual pin ports and theoretical
Intel® 5100 Memory
Controller Hub Chipset
®
INTx
5100 MCH Chipset configuration mechanism. For specific
Button
I/O extender 1
Slot 2
LED
FSB0
Slot 3
Button
1
LED
(P2P bridge, HPC)
for the I/O PCI Hot Plug* operations.
PEX Root Port
100 kHz SMBus
Intel
VPP
®
MSI
5100 MCH Chipset—Functional Description
FSB1
Board Power
Manager
Section 3.7, “Detailed
Order Number: 318378-005US
Figure
Slot 14
A2 A1 A0
Button
I/O extender 7
LED
53. However,
Slot 15
Button
July 2009
LED