HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 246

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.11.23.4
Intel
Datasheet
246
1. The lower DW could contain the address of the previous descriptor while the upper DW contains
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the address of the next descriptor and hence the effective address may be garbled due to the
asynchronous nature between the software read and the chipset update.
5100 Memory Controller Hub Chipset
The Channel Status Register records the address of the last descriptor completed by
the DMA channel. Note that software could read the register any time when the chipset
is updating the status of the descriptor. To prevent coherency issues, when reading the
mismatched lower/upper 32-bits of this register
of the address when the lower DW is read, such that a subsequent read of the upper
DW provides the rest of the higher address returned by the prior lower DW read. The
chipset will guarantee consistency during the data transfer to the latched register and
synchronize concurrent events. The software should issue only 32-bit (DW) reads to
the CHANSTS registers. Any other read length less than 32-bits (e.g., reading just one
byte) will result in indeterministic behavior. Similarly CB BAR MMIO reads of 64-bit in
length will also return indeterministic data and is not preferred since the internal data
path cannot handle sizes larger than one DW.
CHAINADDR[3:0] - Descriptor Chain Address Register
This register is written by the processor or I/O agent to specify the first descriptor to be
fetched by the DMA channel. This address will be checked and FERR/NERR*DMA4 error
will be set by the DMA Engine during execution, i.e., when the initial descriptor is
fetched. The error will also be logged in the CHANERR.Chn_addr_val_err register field.
Offset:
5
4
3
2:0
Offset:
63:0
Bit
Bit
RV
RO
RO
RO
RW
Attr
Attr
204h, 184h, 104h, 84h
20Ch, 18Ch, 10Ch, 8Ch
0
0
0
011
0h
Default
Default
Reserved
Soft_err: Soft Error
The hardware sets this bit when it detects an error that it was able to correct and
resets this bit immediately after it writes the Channel Status to the location
specified by CHANCMP.
Soft error detection is not supported by Intel
to 0.
Unaffil_err: Unaffiliated Error
The hardware sets this bit when it detects an unaffiliated error and resets this bit
immediately after it writes the Channel Status to the location specified by
CHANCMP.
Unaffiliated error detection is not supported by Intel
hardwired to 0.
DMA_trans_state: DMA Transfer Status
The DMA Engine sets these bits indicating the state of the current DMA transfer. The
cause of an abort can be either error during the DMA transfer or invoked by the
controlling process via the CHANCMD register defined in
000 - Active
001 - Completed, DMA Transfer Done (no hard errors)
010 - Suspended
011 - Halted, operation aborted (refer to Channel Error register for further detail)
Desc_Addr: Descriptor Address
This 64 bit field marks the address of the first descriptor to be fetched by the DMA
channel. The least significant 6 bits must be zero for the address to be valid.
Note:
A value of zero to the “Desc_Addr” field is considered illegal and will be
considered as a Fatal error.
Intel
1
, the chipset must latch the upper DW
Description
Description
®
5100 MCH Chipset—Register Description
®
5100 MCH Chipset and is hardwired
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Order Number: 318378-005US
5100 MCH Chipset and is
Section 3.11.23.5
July 2009