HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 232

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.11.19
Intel
Datasheet
232
®
5100 Memory Controller Hub Chipset
PEXDEVCTRL - Device Control Register
Device:
Function:
Offset:
25:18
17:15
14
13
12
11:9
8:6
5
4:3
2:0
Device:
Function:
Offset:
15
14:12
11
10
Bit
Bit
RO
RV
RO
RO
RO
RO
RO
RO
RO
RO
RV
RO
RW
RO
Attr
Attr
8
0
70h
8
0
74h
00h
0h
0
0
0
000
000
0
00
000
0
000
1
0
Default
Default
CSPLV: Captured Slot Power Limit Value
This field applies only to upstream ports. Hardwired to 0h
Reserved
PIPD: Power Indicator Present
The DMA Engine is an integrated device and therefore, an Power Indicator does not
exist. Hardwired to 0h
AIPD: Attention Indicator Present
The DMA Engine is an integrated device and therefore, an Attention Indicator does
not exist. Hardwired to 0h
ABPD: Attention Button Present
The DMA Engine is an integrated device and therefore, an Attention Button does not
exist. Hardwired to 0h
EPL1AL: Endpoint L1 Acceptable Latency
The DMA Engine device is not implemented on a physical PCI Express* link and
therefore, this value is irrelevant. Hardwired to 0h
EPL0AL: Endpoint L0s Acceptable Latency
The DMA Engine device is not implemented on a physical PCI Express* link and
therefore, this value is irrelevant. Hardwired to 0h
ETFS: Extended Tag Field Supported
The DMA Engine device does not support extended tags. Hardwired to 0h
PFS: Phantom Functions Supported
The DMA Engine device does not support Phantom Functions. Hardwired to 0h
MPLSS: Max_Payload_Size Supported
This field indicates the maximum payload size that the CB integrated device can
support.
000: 128 bytes max payload size
others- Reserved
Reserved
MRRS: Max_Read_Request_Size
Since the DMA Engine device does not issue read requests on a PCI Express*
interface, this field is irrelevant. Hardwired to 0h
ENNOSNP: Enable No Snoop
1: Setting this bit enables the DMA Engine device to issue requests with the No
Snoop attribute.
0: Clearing this bit behaves as a global disable when the corresponding capability is
enabled for source/destination snoop control in the DMA’s descriptor’s Desc_Control
field.
APPME: Auxiliary Power PM Enable
The DMA Engine device does not implement auxiliary power so setting this bit has
no effect. Hardwired to 0h
Intel
Description
Description
®
5100 MCH Chipset—Register Description
Order Number: 318378-005US
July 2009