HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 136

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.10
3.8.10.1
Intel
Datasheet
136
®
5100 Memory Controller Hub Chipset
PCI Express* Message Signaled Interrupts (MSI) Capability
Structure
Message Signaled Interrupts (MSI) is an optional feature that enables a device to
request service by writing a system-specified message to a system-specified address in
the form of an interrupt message. The transaction address (e.g., FEEx_xxxxh) specifies
the message destination and the transaction data specifies the message. The MSI
mechanism is supported by the following registers: the MSICAPID, MSINXPTR,
MSICTRL, MSIAR and MSIDR register described below.
MSICAPID[7:2,0] - MSI Capability ID
Device:
Function:
Offset:
Device:
Function:
Offset:
21:16
14:13
12:9
7:2
1:0
7:0
Bit
Bit
22
15
8
Attr
RWCST
RO
RWST
Attr
RW
RO
RO
RO
RV
RV
7-2, 0
0
54h
7-2, 0
0
58h
Default
05h
Default
0h
0h
0h
0h
0h
0h
0h
0h
CAPID: Capability ID
Assigned by PCI-SIG for message signaling capability.
B2B3S: B2/B3 Support
This field is hardwired to 0h as it does not apply to PCI Express*.
Reserved.
PMESTS: PME Status
This PME Status is a sticky bit. When set, the PCI Express* port generates
a PME internally independent of the PMEEN bit defined below. Software
clears this bit by writing a ‘1’ when it has been completed.
As a root port, the Intel
it never generates a PME internally independent of the PMEEN bit.
DSCL: Data Scale
This 2-bit field indicates the scaling factor to be used while interpreting the
“data_scale” field.
DSEL: Data Select
This 4-bit field is used to select which data is to be reported through the
“data” and the “Data Scale” fields.
PMEEN: PME Enable
This field is a sticky bit and when set enables PMEs generated internally to
appear at the ICH9R through the “Assert(Deassert)_PMEGPE”message.
This has no effect on the Intel
generate PME events internally
Reserved
PS: Power State
This 2-bit field is used to determine the current power state of the function
and to set a new power state as well.
00: D0
01: D1 (reserved)
10: D2 (reserved)
11: D3_hot
If Software sets this to D1 or D2, then the power state will default to D0.
Intel
®
5100 MCH Chipset will never set this bit, because
®
Description
®
5100 MCH Chipset—Register Description
Description
5100 MCH Chipset since it does not
Order Number: 318378-005US
July 2009