HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 350

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.20.3.2
5.20.3.3
Intel
Datasheet
350
®
5100 Memory Controller Hub Chipset
Byte Count Field
The byte count field indicates the number of bytes following the byte count field when
performing a write or when setting up for a read. The byte count is also used, when
returning data, to indicate the number of bytes (including the status byte) which are
returned prior to the data. Note that the byte count is only transmitted for block type
accesses on SMBus. SMBus word or byte accesses do not use the byte count.
Address Byte 3 Field
This field should be programmed with the bus number of the desired configuration
register in the lower five bits for a configuration access. For a memory-mapped access,
this field selects which memory-map region is being accessed. There is no status bit to
poll to see if a transfer is in progress; clock stretch is used to guarantee the transfer is
truly complete.
The MCH does not support access to other logical bus numbers via the SMBus port. All
registers “attached” to the SMBus have access to all other registers that are on logical
bus#0. The MCH makes use of this knowledge to implement a modified usage of the
Bus Number register providing access to internal registers outside of the PCI
compatible configuration window.
Position
Position
3:2
1:0
7:0
7
6
5
4
Begin Transaction Indicator.
0 = Current transaction is NOT the first of a read or write sequence.
1 = Current transaction is the first of a read or write sequence. On a single transaction sequence
End Transaction Indicator.
0 = Current transaction is NOT the last of a read or write sequence.
1 = Current transaction is the last of a read or write sequence. On a single transaction sequence
Address Mode. Indicates whether memory or configuration space is being accessed in this SMBus
sequence.
0 = Memory Mapped Mode
1 = Configuration Register Mode
Packet Error Code (PEC) Enable. When set, each transaction in the sequence ends with an extra
CRC byte. The MCH would check for CRC on writes and generate CRC on reads. PEC is not
supported by the MCH.
0 = Disable
1 = Not Supported
Internal Command Size. All accesses are naturally aligned to the access width. This field specifies
the internal command to be issued by the SMBus slave logic to the MCH core.
00 = Read Dword
01 = Write Byte
10 = Write Word
11 = Write Dword
SMBus Command Size. This field specifies the SMBus command to be issued on the SMBus. This
field is used as an indication of the length of the transfer so that the slave knows when to expect
the PEC packet (if enabled).
00 = Byte
01 = Word
10 = DWord
11 = Reserved
Byte Count. Number of bytes following the byte count for a transaction.
this bit is set along with the End Transaction Indicator.
this bit is set along with the Begin Transaction Indicator.
Description
Description
Intel
®
5100 MCH Chipset—Functional Description
Order Number: 318378-005US
July 2009