HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 73

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
Table 28.
Table 29.
3.5
3.5.1
July 2009
Order Number: 318378-005US
MCH
MCH
MCH
MCH
MCH
MCH
Component
Address Mapping, Memory
Control, Error Logs
FSB Error Registers
PCI Express* Port 2-3
PCI Express* Port 4-5
PCI Express* Port 6-7
PCI Express* Port 4-7
Functions Specially Handled by Intel
(Sheet 2 of 2)
To comply with the PCI Local Bus Specification, Rev. 2.3, accesses to non-existent
functions, registers, and bits will be master aborted. This behavior is defined in
Table 29, “Access to “Non-Existent” Register Bits.”
Access to “Non-Existent” Register Bits
I/O Mapped Registers
There are only two I/O addresses that affect the Intel
first address is the DWORD location (CF8h) that references a read/write register named
CONFIG_ADDRESS. The second DWORD address (CFCh) references a read/write
register named CONFIG_DATA. These two addresses are used for the PCI CFCh/CF8h
configuration access mechanism.
CFGADR: Configuration Address Register
CFGADR is written only when a processor I/O transaction to I/O location CF8h is
referenced as a DWord; a Byte or Word reference will not access this register, but will
generate an I/O space access. Therefore, the only I/O space taken up by this register is
the DWORD at location CF8h. I/O devices that share the same address but use BYTE or
WORD registers are not affected because their transactions will pass through the host
bridge unchanged.
The CFGADR register contains the Bus Number, Device Number, Function Number, and
Register Offset for which a subsequent CFGDAT access is intended. The mapping
between fields in this register and PCI Express* configuration transactions is defined by
Table 27, “Configuration Address Bit Mapping.”
Devices listed in
Handled by Intel® 5100 Memory Controller Hub
Chipset,”
Devices listed in
Handled by Intel® 5100 Memory Controller Hub
Chipset,”
“Register Definitions”
Reserved bits in registers
Register Group
but to functions not listed
but to registers not listed in
®
5100 MCH Chipset
Table 28, “Functions Specially
Table 28, “Functions Specially
Access to
65F0h
65F0h
65F7h
65F8h
65F9h
65FAh
DID
Section 3.8,
16
16
2
4
6
4
Device
®
Have no effect
Have no effect
Software must read-
modify-write to preserve
the value
5100 Memory Controller Hub Chipset
Function
1
2
0
0
0
0
Writes
x8 mode. Only port 2 is active
x8 mode. Only port 4 is active
x8 mode. Only port 6 is active
x16 mode. Only port 4 is active
Intel
®
5100 MCH Chipset state. The
®
5100 Memory Controller Hub Chipset
MCH returns all ones
MCH returns all zeroes
MCH returns all zeroes
Comment
Reads
Datasheet
73