HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 338

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.17.4.12
5.17.4.13
5.17.4.14
Intel
Datasheet
338
®
5100 Memory Controller Hub Chipset
Lock Support
For legacy PCI functionality, the MCH supports bus locks through an explicit sequence
of events. The MCH can receive a locked transaction sequence (Read-Write or Read-
Read-Write-Write) on a processor interface directed to a PCI Express*-to-PCI bridge.
Note that native PCI Express* devices are prohibited from supporting bus locks
according to the PCI Express* Base Specification, Rev. 1.0a.
The PCI Express* interface cluster must support the following capabilities:
The Intel
native PCI Express* endpoint, which will return an unsupported request (UR) status
response. Operation is not guaranteed, if a lock to a native PCI Express* device is
issued. Locks to PCI through PCI Express* will still be supported.
Peer-to-peer Transactions
Peer-to-peer support is defined as transactions which initiate on one I/O interface and
target another without going through main memory. The MCH supports peer-to-peer
transactions only for memory and I/O transactions. Any PCI Express* interface can be
the source or destination of a peer-to-peer transaction. Peer-to-peer transactions are
not observed on any interface except the target and destination (they are not snooped
by the processors).
Peer-to-peer traffic between the PCI Express* ports must sustain the full write
bandwidth (depending on the PCI Express* port configuration). For Peer-to-peer reads,
the delivered bandwidth is a function of the round trip read completion latency.
Inbound coherent transactions and peer-to-peer transactions must maintain PCI
Express* ordering rules between each other. Peer-to-peer transactions follow inbound
ordering rules until they reach the head of the inbound queue. Once the transaction
reaches the head of the inbound queue, the MCH routes the transaction to the next
available slot in the outbound queue where PCI ordering is maintained until the end of
the transaction. The MCH does not support peer-to-peer transactions where the source
and destination are on the same PCI Express* interface.
Peer-to-peer Configuration Cycles
The MCH supports peer-to-peer PCI Express* configuration cycles through Type0 and
Type1 configuration requests. For this feature to be enabled, the configuration register
bit PEXCTRL.DIS_INB_P2PCFG, PEXCTRL[7:2, 0], PCI Express* Control Register, for
the respective ports has to be cleared. If an inbound peer-to-peer configuration cycle is
received by the MCH, the bus number, device number, function number and register
number are compared.
If the resulting comparison is such that the bus number does not fall in the range of the
primary to subordinate bus number register, the configuration cycle is completed with
an Unsupported Request completion status.
If the comparison targets the bus indicated by a secondary bus register, then the MCH
translates the configuration cycle into a Type 0.
If the comparison targets the bus such that (secondary bus < bus_number <=
subordinate_bus), then the MCH translates the configuration cycle into a Type 1.
• Block all transactions on the PCI Express* ports (when the lock targets another
• Generate a locked read request to the target PCI Express* port
• Unlock the locked PCI Express* port
port)
®
5100 MCH Chipset lock flow will not complete if a memory read is sent to a
Intel
®
5100 MCH Chipset—Functional Description
Order Number: 318378-005US
July 2009