HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 308

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.12.6
5.12.7
5.12.7.1
5.12.7.2
5.13
Note:
Intel
Datasheet
308
®
5100 Memory Controller Hub Chipset
When the MCH accepts these PCI Express* interrupt messages, it aggregates and
passes the corresponding “Assert_INTx” messages to the ICH9R’s I/OAPIC with from
the PCI Express* ports (wired-OR output transitions from 0->1) mechanism. When the
corresponding Deassert_INTx message is received at all the PCI Express* ports (wired-
OR output transitions from 1->0), the “Deassert_INTx” message is sent to ESI port.
End-of-Interrupt (EOI) Support
The EOI is a specially encoded processor bus transaction with the interrupt vector
attached. Since the EOI is not directed, the MCH will broadcast the EOI transaction to
all I/O(x)APICs. The SC.PEXCTRL.DIS_APIC_EOI bit per PCI Express* port can be used
to determine whether an EOI needs to be sent to a specific port.
Error Handling
Table 123, “Intel® 5100 Memory Controller Hub Chipset Error List”
detected on ESI through the standard PCI Express* and Advanced error reporting
mechanism.
Inbound Errors
In general, if an inbound read transaction results in a Master Abort (unsupported
request), the compatibility interface cluster returns a Master Abort completion with
data as all ones. Likewise, for a Target Abort condition, the ESI cluster returns a Target
Abort completion with data as all ones. If a read request results in a Master or Target
Abort, the MCH returns the requested number of data phases with all ones data.
Master aborted inbound writes are dropped by the MCH, the error is logged, and the
data is dropped.
If the MCH receives an inbound unsupported Special Cycle message it is ignored and
the error condition is logged. If the completion required bit is set, an Unsupported
Special Cycle completion is returned.
Outbound Errors
It is possible that the compatibility interface cluster will receive an error response for
an outbound request. This can include a Master or Target Abort for requests that
required completions. The MCH might also receive an “Unsupported Special Cycle”
completion.
PCI Express* Ports
The Intel
These are:
There is no PCI Express* port designated as Port 1.
The ESI port is the primary interface to the ICH9R. The Intel
supports six general purpose x4 PCI Express* ports. These ports are combinable to
form three high performance x8 ports. The MCH also supports the combination of Port
4 through Port 7 to form a high performance x16 graphics PCI Express* port.
The following sections describe the characteristics of each of these port classes in
detail.
• Enterprise South Bridge Interface (ESI), Port 0
• DMA Engine/General purpose ports, Port 2, Port 3, Port 4, Port 5, Port 6, and Port 7
®
5100 MCH Chipset contains two classes of PCI Express* derived ports.
Intel
®
5100 MCH Chipset—Functional Description
®
5100 MCH Chipset
Order Number: 318378-005US
describes the errors
July 2009