HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 328

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 101.
5.16.3.2
5.16.3.3
Intel
Datasheet
328
®
5100 Memory Controller Hub Chipset
Table 101
INTRCTRL Interpretation
DMA Engine Interrupt Handler
The ISR dispatches the DMA Engine interrupt handler whenever any channels need
servicing. The handler performs the following steps.
The DMA Engine Interrupt handler calls each of the appropriate interrupt handlers and
when they are finished, it may re-read the ATTNSTATUS (step 3.) to see if any new
interrupts are pending, and if so, repeats the process. When all interrupts have been
serviced, the DMA Engine interrupt handler sets the master interrupt enable and ends.
Another possibility is for the DMA Engine Interrupt handler to dispatch the appropriate
channel interrupt handlers, set the master interrupt enable and end (i.e., skip step 3.,
ending as soon as it dispatches the appropriate channel handlers).
Note that the chipset automatically sets the channel’s Interrupt Disable bit in the
CHANCTRL register when an interrupt event sets the corresponding ATTNSTATUS bit.
Thus, step
callback had processed the interrupts, cleared the Interrupt Disable bit, and another
interrupt event occurred.
Channel Interrupt Callback
The channel’s interrupt handler reads the channel’s status (CHANSTS), processes the
completions, process errors (CHANERR), and then re-enables the channel’s interrupt by
clearing the channel’s Interrupt Disable bit in the CHANCTRL register. After the Channel
Interrupt
1. Read the Attention Status (ATTNSTATUS) register to determine which channels
2. Call the respective channel’s interrupt routine.
3. Re-read the ATTNSTATUS register to determine if any additional channels require
4. Set the master interrupt enable in INTRCTRL
5. Terminate.
• If the ISR reads the INTRCTRL register and Master Interrupt Enable and Interrupt
Master
Enable
by setting the Master Interrupt Enable and returns without dispatching the DMA
Engine Interrupt Handler.
Status are both set, this indicates this is the first ISR and it dispatches the DMA
Engine interrupt handler, which is responsible for re-enabling interrupts by setting
the master interrupt enable.
require attention.
attention.
a.
b. If all zeros, continue with next step
1
1
0
If not all zeros, go to step
illustrates the ISR’s reaction to reading INTRCTRL.
Interrupt
2.
Status
prevents step
0
1
x
Spurious interrupt
Valid interrupt
Interrupt already being
handled
Implied Meaning
3.a
for the same channel, unless the channel interrupt
2.
and repeat.
Intel
Set Master Interrupt Enable and return (no interrupt)
Dispatch DMA Engine Interrupt Handler and return -
Interrupt handler will re-enable interrupts
return (no interrupt)
®
5100 MCH Chipset—Functional Description
ISR Actions
Order Number: 318378-005US
July 2009