HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 132

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.8.33
3.8.8.34
Intel
Datasheet
132
®
5100 Memory Controller Hub Chipset
PEXCTRL3[7:2,0] - PCI Express* Control Register 3
This is an additional control register for PCI Express* port specific debug/defeature
operations for RAS.
PEXGCTRL - PCI Express* Global Control Register
This 32-bit global register in the MCH implements chipset specific operations for
generalized control of all PCI Express* events and activity such as Power Management,
PCI Hot Plug*. There is only one register for all PCI Express* ports and DMA Engine
device that controls related I/O operations.
Device:
Function:
Offset:
7:5
3:1
Bit
4
0
if (port0)
RV else
{RWO}
endif
Attr
RW
RV
RV
7-2, 0
0
4Dh
Default
0h
0
1
0
Reserved
PORTENABLE: PCI Express* port enable control
1: The PCI Express* port can be enabled by software and is available for
use
0: The PCI Express* port is disabled and not available. This setting
disables the underlying port logic and associated PCI Express* x4 lanes,
completely removing the port from register configuration space.
Reserved (See RV definitions
MSIRASERREN: MSI RAS Error Enable
1: Enables MSI messages to be sent to the root complex for RAS error
events on PCI Express ports.
0: Disables sending of MSI messages for RAS error events on PCI Express
ports to the root complex.
Note that for MSI RAS Error messages to be sent, both MSIRASERREN and
MSICTRL[7:2] MSIEN bits defined in
Intel
®
Section 3.1, “Register
5100 MCH Chipset—Register Description
Description
Section 3.8.10.3
Order Number: 318378-005US
Terminology”.)
have to be set.
July 2009