HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 216

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.10
Table 70.
Intel
Datasheet
216
®
5100 Memory Controller Hub Chipset
PEXDEVSTS
MSICTRL
PEXSTS
PEXCAP
DID
SID
DMA Engine Configuration Registers
Device 8, Function 0, DMA Engine Configuration Map
The VID and DID of the DMA Engine are defined in
Identification Register”
RID is defined in
register appears in
can be found in
HDR
CCR
CB_ERR_DOCMD
PEXDEVCAP
DMACTRL
CB_BAR
PMCAP
PMCSR
MSIDR
MSIAR
MSINXPTR
PEXNXPTR
INTP
PEXDEVCTRL
Section 3.8.1.6, “SVID - Subsystem Vendor Identification Register.”
PEXCMD
Section 3.8.1.3, “RID - Revision Identification Register”
SVID
VID
Section 3.8.1.5, “HDR - Header Type Register.”
MSICAPID
PEXCAPID
CAPPTR
and
INTL
RID
Section 3.8.1.2, “DID - Device Identification Register.”
0Ch
1Ch
2Ch
3Ch
4Ch
5Ch
6Ch
7Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
40h
44h
48h
50h
54h
58h
60h
64h
68h
70h
74h
78h
FERR_CHANC
MD
Intel
FERR_TRANSFER_SIZE
®
Section 3.8.1.1, “VID - Vendor
5100 MCH Chipset—Register Description
FERR_DESC_CTRL
FERR_CHANCMP
FERR_CHANSTS
FERR_DADDR
FERR_NADDR
FERR_SADDR
Order Number: 318378-005US
NERR_CHANERR
FERR_CHANERR
The SVID and SID
while the HDR
July 2009
The
DCh
8Ch
9Ch
A0h
A4h
A8h
ACh
B0h
B4h
B8h
BCh
C0h
C4h
C8h
CCh
D0h
D4h
D8h
ECh
80h
84h
88h
90h
94h
98h
E0h
E4h
E8h
F0h
F4h
F8h
FCh