HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 256

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.12.0.15
3.12.0.16
3.12.0.17
Intel
Datasheet
256
®
5100 Memory Controller Hub Chipset
BR_MEM_BASE[3:2] - Bridge Memory Base Register
The BR_MEM_BASE and BR_MEM_LIMIT registers identifies the MMIO address range for
PCI devices served by the PCI Express* port 2 or 3. These registers are a copy of the
PCI Express* configuration registers for the port for which this set of per-port functions
are valid. The corresponding port’s PEXCMD.MSE register field will gate the output of
this register during read operations. This enables software to determine which I/O
devices are downstream of this port and thus can use this set of per-port DMA Engine
resources. Note that only one of those down stream devices can use Stream Priority
capability at a time (see In-Use bit).
BR_MEM_LIMIT[3:2] - Bridge Memory Limit Register
BR_PMEM_BASE[3:2] - Bridge Prefetchable Memory Base Register
The BR_PMEM_BASE along with BR_PMEM_LIMIT, BR_PBASE_UPPER32 and
BR_PLIMIT_UPPER32 registers defined below identify the prefetchable address range
for PCI Express* devices served by the respective port (64-bit addressable space).
These registers are a copy of the PCI Express* port’s configuration registers for which
this set of per-port functions are valid. The corresponding port’s PEXCMD.MSE register
field will gate the output of this register during read operations. S/W can determine
which I/O devices are downstream of this port and thus can use this set of per-port
DMA Engine resources. Note that only one of those down stream devices can use
Stream Priority capability at a time (see In-Use bit).
Offset:
Offset:
Offset:
15:0
15:0
15:0
Bit
Bit
Bit
Attr
Attr
Attr
RO
RO
RO
3A0h, 320h
3A2h, 322h
3A4h, 324h
Default
Default
Default
0h
0h
0h
BR_MBASE: Bridge Memory Base Register
This is a copy of the Memory Base Register of the virtual P2P bridge for the PCI
Express* port with which it is associated (port 3 or port 2). See also
Section
BR_MLIM: Bridge Memory Limit Register
This is a copy of the Memory Limit Register of the virtual P2P bridge for the PCI
Express* port with which it is associated (port 3 or port 2). Refer to
Section 3.8.8.17
BR_PMBASE: Bridge Prefetchable Memory Base Register
This is a copy of the Prefetchable Memory Base Register of the virtual P2P bridge for
the PCI Express* port with which it is associated (port 3 or port 2). Refer to
Section 3.8.8.18
If PEXCMD.MSE==0 for the virtual P2P port, then this register, when read, returns a
value of 0h else return contents of BR_PMBASE field.
3.8.8.16.
Intel
Description
Description
Description
®
5100 MCH Chipset—Register Description
Order Number: 318378-005US
July 2009