HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 119

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.8.15
July 2009
Order Number: 318378-005US
SECSTS[7:2] - Secondary Status
SECSTS is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side (i.e., PCI Express* side) of the “virtual” PCI-to-PCI
bridge embedded within MCH.
Device:
Function:
Offset:
Device:
Function:
Offset:
10:9
3:0
Bit
Bit
15
14
13
12
11
8
®
RWC
RWC
RWC
RWC
RWC
RWC
Attr
Attr
RO
RO
5100 MCH Chipset
2-3, 4-7
0
1Dh
2-3, 4-7
0
1Eh
Default
Default
0h
00
0
0
0
0
0
0
IOLCAP: I/O Address Limit Capability
0h – 16 bit I/O addressing, (supported)
1h – 32 bit I/O addressing,
others - Reserved.
The MCH does not support 32 bit I/O addressing, so these bits are hardwired
to 0.
SDPE: Detected Parity Error
This bit is set by the Intel
TLP in the PCI Express* port regardless of the state the Parity Error Response
bit (in the BCTRL.PRSPEN register). This corresponds to IO4 as defined in
Table 123, “Intel® 5100 Memory Controller Hub Chipset Error List.”
SRSE: Received System Error
This bit is set by the MCH when it receives a ERR_FATAL or ERR_NONFATAL
message. See
that BCTRL.BCSERRE is not a gating item for the recording of this error on the
secondary side.)
SRMAS: Received Master Abort Status
This bit is set when the PCI Express* port receives a Completion with
“Unsupported Request Completion” Status.
SRTAS: Received Target Abort Status
This bit is set when the PCI Express* port receives a Completion with
“Completer Abort” Status.
SSTAS: Signaled Target Abort
This bit is set when the PCI Express* port completes a request with
“Completer Abort” Status when the PEXSTS.RTA is set since the MCH acts as a
virtual PCI bridge and passes the completion abort from the primary to the
secondary side.
Note however that the MCH will not set the SSTAS field directly on the
secondary side since all requests are passed upstream through the primary
side to the internal core logic for decoding.
SDEVT: DEVSEL# Timing
Not applicable to PCI Express*. Hardwired to 0
SMDPERR: Master Data Parity Error
This bit is set by the PCI Express* port on the secondary side (PCI Express*
link) if the Parity Error Response Enable bit (PRSPEN) in
“BCTRL[7:2] - Bridge Control Register”
conditions occurs:
If the Parity Error Response Enable bit is cleared, this bit is never set. Refer to
Table 53, “Intel® 5100 Memory Controller Hub Chipset PEXSTS and SECSTS
Master/Data Parity Error RAS Handling”
handling matrix in the Intel
• The PCI Express* port receives a Completion marked poisoned
• The PCI Express* port poisons a write Request
Section 3.8.8.28, “BCTRL[7:2] - Bridge Control Register.”
®
5100 MCH Chipset whenever it receives a poisoned
®
5100 MCH Chipset.
Description
Description
Intel
is set and either of the following two
®
for details on the data parity error
5100 Memory Controller Hub Chipset
Section 3.8.8.28,
Datasheet
(Note
119