HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 268

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

4.3.7.2
Note:
4.3.7.3
4.3.7.4
4.3.7.5
4.3.8
4.3.8.1
Intel
Datasheet
268
®
5100 Memory Controller Hub Chipset
For PCI Hot Plug* I/O APIC support, it is recommended that software use the standard
MMIO range to communicate with the Intel
this, the Intel
Hub.XAPIC_BASE_ADDRESS_REG must be programmed within the PCI Express* device
MMIO region.
Inbound accesses to this memory range should also be routed to the I/O APIC
controllers. This could happen if software configures MSI devices to send MSIs to an I/
O APIC controller.
High SMM Range
If high SMM space is enabled by EXSMRC.H_SMRAME, then requests to the address
range from FEDA 0000h to FEDB FFFFh will be aliased down to the physical address of
A 0000h to B FFFFh. The HIGHSMM space allows cacheable accesses to the compatible
(legacy) SMM space. In this range, the chipset will accept EWBs (BWLs) regardless of
the SMMEM# pin. Also, if there is an implicit write back (HITM with data), the chipset
will update memory with the new data (regardless of the SMMEM# pin). Note that if the
HIGHSMM space is enabled, the aliased SMM space of 0A 0000h - 0B FFFFh will be
disabled.
In order to make cacheable SMM possible, the chipset must accept EWBs (BWLs) and
must absorb IWB (HITM) data regardless of the condition of the SMMEM# pin. Because
of this, care must be used when attempting to cache SMM space. The chipset/platform
cannot protect against processors who attempt to illegally access SMM space that is
modified in another processor’s cache. Any software that creates such a condition (for
example, by corrupting the page table) will jeopardize the protective properties of
SMM.
Interrupt Range
Requests to the address range FEE0 0000h to FEEF FFFFh are used to deliver
interrupts. Memory reads or write transactions to this range are illegal from the
processor. The processor issues interrupt transactions to this range. Inbound interrupt
requests from the PCI Express* devices in the form of memory writes are converted by
the MCH to processor bus interrupt requests.
Reserved Ranges
The Intel
interrupt/reserved range (FEC0 0000h - FEFF FFFFh) which are not specified. This can
be done by sending the request to the compatibility bus (ESI) to be master aborted.
Firmware Range
The Intel
FFFF FFFFh. Requests in this range are directed to the Compatibility Bus. The ICH9R
will route these to its FWH interface. This range is accessible from any processor bus.
High Extended Memory
This is the range above 4 GB. The range from 4 GB to SC.MIR.LIMIT is mapped to
system memory. There can also be a memory mapped I/O region that is located at the
top of the address space. (Just below 1 TB).
System Memory
See
Section 4.3.9, “Main Memory Region”
®
®
5100 MCH Chipset will master abort requests to the addresses in the
5100 MCH Chipset allocates 16 MB of firmware space from FF00 0000h to
®
6700PXH 64-bit PCI Hub.MBAR and/or Intel
®
6700PXH 64-bit PCI Hub. To accomplish
Intel
®
5100 MCH Chipset—System Address Map
®
6700PXH 64-bit PCI
Order Number: 318378-005US
July 2009