HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 97

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.2
3.8.3
Table 50.
July 2009
Order Number: 318378-005US
A write to any of the above registers on the MCH will write to all of them.
SID - Subsystem Identity
This register identifies the system. They appear in every function except the PCI
Express* functions.
Address Mapping Registers
These registers control transaction routing to one of the three interface types (Memory,
PCI Express*, or ESI) based on transaction addresses. The memory mapping registers
in this section are made read-only by the LOCK MEMCONFIG command, see D_LCK bit
Section 3.8.3.8, “SMRAMC - System Management RAM Control Register.”
particular ports of a given interface type are defined by the following registers.
Address Mapping Registers
1. Any request not falling in the above ranges will be subtractively decoded and sent to ICH9R via the ESI
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
15:0
Memory
PCI Express*
ESI
15:0
Bit
Bit
Interface
Type
RWO
Attr
RWO
Attr
®
5100 MCH Chipset
0, 8
0
2Ch
16
0, 1, 2
2Ch
21, 22
0
2Ch
0, 8
0
2Eh
16
0, 1, 2
2Eh
21, 22
0
2Eh
Default
8086h
8086h
Default
MIR, AMIR, PAM, SMRAM, EXSMRC, EXSMRAMC, TOLM, EXSMRTOP
MBASE/MLIM (devices 2-7)
PMBASE/PMLIM (devices 2-7)
PMBU/PMBL (devices 2-7)
IOBASE/IOLIM (devices 2-7)
SBUSN, SUBUSN (devices 2-7)
BCTRL, HECBASE, PEXCMD (devices 2-7)
Subtractive decode
Vendor Identification Number.
The default value specifies Intel. Each byte of this register will be writable once.
Second and successive writes to a byte will have no effect.
Subsystem Identification Number:
The default value specifies Intel. Each byte of this register will be writable once.
Second and successive writes to a byte will have no effect.
1
(device 0)
Address Routing Registers
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Routing to
Datasheet
97